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TaN was widely used as Cu diffusion barrier in CMOS Cu-BEOL technology, in which it was removed by CMP process. Some work was done on TaN etch by Br/Cl-based gas for metal gate application. But seldom work was done for TaN etch in CF-based gas. In this work TaN etching in CF4/CHF3 gas was investigated on CVD alpha-Si substrate for CMOS compatible MEMS/Sensor application. To avoid resist poisoning...
A micromachining process has been developed to create high impedance and low loss high aspect ratio coplanar waveguide (HARC) on low resistivity silicon. The process uses silicon DRIE to create an array of tall mesas that are spaced with a precise pitch. The silicon mesa array is then merged into a single solid SiO2 mesa using thermal oxidation. The solid SiO2 mesa creates a wide dielectric for use...
A silicon micromachining processconductors has been developed to fabricate high aspect ratio CPW (HARC). The micromachining process combines Si DRIE, thermal oxidation, electroplating, and planarization to create tall CPW with Au conductors and SiO2 dielectrics. Si is removed underneath the transmission lines to minimize the field interaction with the substrate which virtually eliminates substrate...
Silicon-on-lattice engineered substrates (SOLES) are SOI substrates with embedded Ge layers that facilitate III-V compound integration for advanced integrated circuits. The new materials integration scheme in SOLES requires the analysis of its thermal stability and diffusion barrier properties. In this study, we report on the successful monolithic integration of CMOS/III-V transistors with a reduced...
In this paper, we proposed a sealing technique for a sealing glass cap with a ceramic substrate by using silica coating liquid to increase the performance of fluid-based inclination sensor in heat-resisting and durability characteristic. The sensor was developed with one-side-electrode-type structure and propylene carbonate was used as electrolyte. The sensor uses capacitance change to detect the...
Effect of the flat band voltage reduction (roll-off) in highly scaled high-k/metal gate stacks is discussed. The proposed mechanism explains the roll-off phenomenon as caused by the metal electrode/high-k dielectric-induced generation of positively charged oxygen vacancies in the interfacial SiO2 layer in the high-k dielectric stack. The model is consistent with the observed roll-off dependency on...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
We have observed new charge trapping phenomena in sub-80-nm DRAM recessed- channel-array-transistor (RCAT) after Fowler-Nordheim (FN) stress. Gate stack process strongly affected the charge trapping and the trap generating in oxide bulk and interface of RCAT. According to the trapped charges and/or the generated traps after FN stress, the data retention time and writing capabilities of DRAM were dramatically...
SOI (silicon-on-insulator) technology has been proposed to improve performance of integrated circuits (ICs) fabricated usually in CMOS (complementary metal-oxide-semiconductor) bulk technology. A SOI wafer consists of a thin monocrystalline Si film over an insulating layer of silicon dioxide (buried oxide - BOX) on a Si substrate playing for traditional IC application a role of a mechanical support...
In this work, we report the demonstration of a novel CMOS process with substrate-strained-SiGe pMOSFET and mechanical-strained Si nMOSFET fabricated on one chip. The device structure combines the advantages of compressively SiGe materials and tensile Si induced by SiN layer to achieve higher carrier mobility. Moreover, due to the separation process of two kind devices, individual MOSFETs was tuned...
High performance Ni-FUSI/HfSiON CMIS with suitable Vth in a wide Lg range is presented. This is accomplished by ion implantation to substrate and phase control of Ni-FUSI gate. Threshold voltage of NiSi-FUSI NMIS is controlled by nitrogen implantation, and that of Ni2Si-FUSI PMIS is controlled by fluorine implantation. It is demonstrated that N/F incorporation can realize 0.2-V-low |Vth|, high carrier...
We have developed a dual metal gate CMOS technology with HfSix for nMOS and Ru for pMOS on HfO2 gate dielectric. These gate stacks show high mobility (100% of universal mobility for electron, 80% for hole at high fields) down to Tinv of 1.7 nm and symmetrical low Vt equivalent to poly-Si/SiO2. As a result, high drive currents of 780 muA/mum and 265 muA/mum at Ioff = 1 nA/mum are achieved for Vdd...
As the conventional scaling of CMOS technology is reaching its physical limitations, new materials and processes hold promise of giving CMOS a new lease on life. In order to turn an opportunity into a reality, the semiconductor industry is confronted with a daunting task of managing and co-integrating an unprecedented confluence of innovative approaches: high-k dielectric materials (HfO2, HfSiON)...
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