The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
We have developed a strain gauge sensor to measure two axial dynamic strain and temperature evolution during ultrasonic flip-chip bonding. The sensor detects strain from change in resistance due to the piezoresistance effect of Si and temperature from change in current-voltage characteristics of pn-junction. The spatial resolution of the sensor is 20 µm. Au planar microbumps were used for the measurement...
Mid-infrared intersubband absorption from p-Ge quantum wells with Sio.sGeo.s barriers grown on a Si substrate is demonstrated from 6 to 9 μm wavelength at room temperature and can be tuned by adjusting the quantum well thickness.
In this work, investigations on stress development in electrically conductive adhesives used as a die-attachment technology for electronic devices are presented. Three electrically conductive adhesives and two measurement techniques were used for investigations. A silicon stress chip with NiCr-thin film metallic strain-gauge structures developed in our group is used for determination of stress development...
Warpage has become a very critical reliability problem for the advanced electronic packaging technique. One or more chips are stacked on the substrates for a device. The device thus contains materials that have different physical properties. The most prominent problem would be the differences in the thermal expansion coefficient for these materials. During fabrication, thermal energy was applied to...
The effects of strain field are studied in Si wafers implanted with heavy iodine and bismuth ions and in multi-quantum well structures. The experimental method of thermally stimulated currents without applied bias is used, and the trapping centres parameters are determined by modelling the discharge curves. In both cases, the strain field produces temperature-dependent parameters of trapping levels...
In order to clarify the source of resonant frequency drift in MEMS resonators, thermal expansion effect of packaging on MEMS devices was investigated. The strain in a silicon plate bonded on an aluminum plate with temperature was precisely measured. Increasing amount of strain in the aluminum plate was as large as 200 micro-strain with increase in only 20 degrees of temperature. The strain in the...
A strong demand of even more compact and reliable power electronic devices has powered in the last years the development of advanced device design techniques. A key role in these techniques is played by the reliability assessment, a procedure that estimates the expected lifetime of power devices according to given mission profiles. The reliability assessment of a low voltage MOSFET working in avalanche...
The macroscopic stress dependence of bipolar junction transistors (BJTs) can be modeled by three transport model parameters as a function of stress: saturation current IS, forward current gain βF, and Early voltage VA. Recent research has shown that Early voltage VA is independent of stress, so it is not discussed in detail in this paper. Unfortunately, accurate extraction of model parameters IS and...
We present the carrier-transport, optical and structural properties of InP deposited on Si by Epitaxial Lateral Overgrowth (ELOG) in a Low Pressure-Hydride Vapor phase epitaxy (LP-HVPE). Hall measurements, micro photoluminescence (μ-PL) and X-ray diffraction (XRD) were used to study the above-mentioned respective properties at room temperature. It is the first time that electrical properties of ELOG...
SiGe/Si quantum-well nanomembranes, where stress due to lattice mismatch is relaxed via elastic strain sharing rather than defect formation, are developed and their potential for far-infrared intersubband device applications is demonstrated.
Strain engineering has become indispensable for electron and hole mobility improvement of ULSIs as scaling down of device dimension. In order to realize the high performance strained Si layer, it is very important to create a defect-free relaxed Si1-x-yGexCy layer. In the previous work, it was found that, by stripe-shape patterning unstrained Si cap layer/compressive-strained Si1-xGex layer/Si(100)...
In this work we compare techniques to measure the stress in Cu through silicon via's (TSV's) and study the stress as a function of post-plating anneal time and temperature. Our results show that each technique was able to measure the stresses with good agreement. However, wafer curvature was limited to measuring the in-plane stress and the top down Raman spectroscopy geometry is dominated by the out-of-plane...
Subthreshold measurements can reveal key device parameters. We present a method to identify the region of the transfer characteristic where the drain current is affected by neither parasitic off-state leakage nor strong inversion current. Then we employ this method to obtain the conduction band edge shift for FinFETs with various fin widths using temperature dependent transfer characteristics. The...
Aluminum nitride (AlN) is a promising material for harsh environment sensing applications due to its piezoelectric effect and mechanical stability at high temperatures. In this work, AlN double-ended tuning forks (DETF) are presented as a transduction element to measure mechanical loads by observing the resonance frequency shift. The fabrication process of the MEMS devices including the bonding step...
Due to high performance demand, the dimensions of chips should be reduced so the stacked 3D-ICs are introduced into semiconductor industry. For small substrate dimensions and high interconnects requirements, the FR-4 substrates are substituted by the Si substrates. The Si chips and substrates are thinned down. A rigid material like Si suffers much larger thermal stress when the thickness is below...
The manufacturing process of Printed Circuit Boards (PCB) with embedded active components requires several modifications on the build-up layer configuration, including the use of thinner layers and heterogeneous composite materials. From the point of view of second level interconnects the increase in density and complexity of the build-up of electronic board leads to an increase of the total resin-content...
In this work, we studied the fabrication and characterization of strain sensors based on semiconductor materials for high temperature applications: non-stoichometric amorphous silicon carbide (a-SixCy) thin film and SOI (Silicon-On-Insulator) substrates. a-SixCy were deposited onto thermally oxidized (100) Si wafers by plasma enhanced chemical vapor deposition (PECVD) technique using silane (SiH4)...
Wire bonding is still the dominant interconnection technology for power semiconductors in power modules, e.g. for automotive or photovoltaic applications. In the past, many research activities have occurred in the field of reliability of power modules, where the life time of the complete module is affected by bond wire lift offs, heel cracks and other failures. Less effort was spent for investigating...
A novel silicon capacitive temperature sensor implemented with micromachined multilayer cantilevers is presented. The multi-layered sensor structure has been fabricated with SOI wafers by a 4-mask process. Using this structure, the low-power dissipation and wide temperature range can be achieved. For the present sensor, the temperature range is from -70??C to 100??C with the sensitivity of 7 fF/??C...
Through-silicon vias (TSVs) have garnered a lot of interest in recent years because TSV is a key enabling technology for three dimensional (3D) integrated circuit (IC) stacking, silicon interposer technology, and advanced wafer level packaging (WLP). There has been significant effort in TSV fabrication and electrical design. However, considerably less work has been done on thermo-mechanical analysis...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.