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Nanoscale single-electron pumps could serve as the realization of a new quantum standard of electrical current. Here, a silicon quantum dot with tunable tunnel barriers is used as a source of quantized current. By controlling the electrostatic confinement of the dot via purposely engineered gate electrodes, we show that the robustness of the pumping mechanism can be dramatically enhanced and the detrimental...
In this work we calculate the impact of remote SO phonon scattering on the transfer characteristics of gate-all-around Si nanowire transistors. The polar SO phonons are confined to the HfO2/Si interface. Nanowire transistors with two different cross-sections are considered. The results show that the impact on the drain current is of the same order and of the same importance as other commonly used...
We have performed non-equilibrium Green's function simulation of n-type ultra-small V-groove junctionless field-effect transistors (JL-FETs) on a silicon-on-insulator substrate under the ballistic condition. We find that the ON-current is determined mainly by the gap thickness and the subthreshold swing becomes the minimum at a gap-thickness of about 0.6 nm for the gate-length of 7.2 nm.
Threshold voltage shift is a major problem for UMOS device. This study explains how device performance can be affected by silicon defects (interstitial and Vacancy). Interstitial may be induced by epitaxy process or trench process. Interstitial enhances the dopant diffusion. In TCAD simulation interstitial distribution is different for different diffusion model and shows shift in the threshold voltage...
A vertical power MOSFET with the extended trench oxide is proposed. The key feature of this device structure is that the trench oxide, which is set in the side of the device, is extended to n+ substrate. This technique decreases the corner effect of oxide and improves the tradeoff between breakdown voltage (BV) and the specific on-resistance (Ron, sp). Silvaco T-CAD tool is used for the simulation...
Fluctuations of device characteristics due to random discrete dopant (RDD) distribution are numerically investigated in ultra-small Si nanowire transistors. Kinetic Monte Carlo process simulation is performed to obtain realistic RDD distributions, whose effects on the transport characteristics are then analyzed by using a non-equilibrium Green's function (NEGF) method. Fluctuations due to atomic disorder...
For the first time, herein we demonstrate gate-all-around field-effect-transistors having a horizontally suspended nanowire channel. The suspended nanowires were grown using the vapor-liquid-solid technique. The gate-all-around field-effect-transistor exhibited a p-type accumulation mode with desirable performance. To study properties of the connection between the nanowire channels and electrodes,...
L-shaped tunneling field-effect transistors (TFETs) feature high current drivability and abrupt on-off transition. For further improvement of L-shaped TFETs, tunneling regions become n-type doped in this study. The doping concentration of the tunneling regions is optimized. The proposed novel L-shaped TFETs show higher on-current (Ion) and lower subthreshold swing (SS) than conventional L-shaped TFETs.
In modern VLSI designs, assertions play an important role to understand design intention and ensure correctness of designs. In this paper, we consider to generate assertions from simulation results. This assertion extraction is performed by examining whether a logical relation is satisfied among a set of signals. We propose to accelerate it by utilizing a highly parallelized computation performed...
Understanding (and predicting!) the properties of electronic transport in aggressively scaled devices used in VLSI requires a significant departure from 'conventional' approaches used so far which have relied on extrapolations to smaller length scales of models based on bulk band-structure (often a simple 'effective mass') and semiclassical (Boltzmann) transport. In this talk I will discuss some unexpected...
Valence subband structures and hole effective masses of PMOS inversion layer in uniaxial strained Si channel on (110) and (111) Si substrates are studied theoretically based on the 6-band k.p model. The channel direction is chosen as along the 45º direction in the x-y plane, namely, [-1 1 -√2] in the (110) system and [1-√3 1+√3 -2] in the (111) system. Uniaxial stresses considered are applied in the...
We demonstrate a controlled-phase gate for continuous variables using a cluster-state resource of four optical modes. Its nonclassicality is verified through the presence of entanglement at the outputs for product-state inputs of two coherent states.
This paper reviews the definition of innovative enterprises, innovative clusters and innovation resources. Then it develops four mechanisms about the impact of innovative enterprises to innovative clusters on the agglomeration of innovative resources. It also analyzes four pathways for innovative enterprises to affect the diffusion of innovative resources. Finally, it proposes three policy recommendations...
P-doped silicon rich oxide (SRO) /silicon dioxide (SiO2) superlattices, deposited by sputtering method under different substrate temperatures, were treated using conventional furnace annealing or rapid thermal annealing (RTA). Raman and X-ray diffraction (XRD) were used to characterize the samples. Results show larger nanocrystal size is formed by furnace annealing than by RTA. High crystallinity...
Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO2. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer...
We present a generic method for analyzing the effect of process variability in nanoscale circuits. The proposed framework uses kernel and a generic tail probability estimator to eliminate the need for a-priori density choice for the nature of circuit variation. This allows capturing the true nature of the circuit variation from a few random samples of its observed responses. The data-driven, non-parametric,...
This paper presents the probabilistic logic model to compute the probability distribution of the nano gate states. The characterization is based on the Markov random field and statistic physics. The primary logic gates are probabilistically characterized. The effectiveness of the method is demonstrated by a full adder and an 8-bit adder. The analysis shows that the device probability distribution...
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