The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Nowadays, the growing complexity in a wide variety of applications has led to the use of Multiprocessor Systems-on-Chip (MPSoCs). Networks-on-Chip (NoCs) have emerged as a scalable intra-chip communication technology for a high number of processing elements. However, the evolution of MPSoCs shows increasing communication requirements due to the growing number of PEs. This paper presents a novel Network-on-Chip...
The NoC Architecture plays crucial role while designing communication systems for System on Chip (SoC). The NoC architecture is improved over conventional bus, shared bus design and cross bar interconnection architecture for on chip networks. In order to improve the Quality of Service, Congestion, Throughput and latency in NoC, Hexagonal node based architecture is proposed in our previous paper[14]...
Communications systems make heavy use of FPGAs; their programmability allows system designers to keep up with emerging protocols and their high-speed transceivers enable high bandwidth designs. While FPGAs are extensively used for packet parsing, inspection and classification, they have seen less use as the switch fabric between network ports. However, recent work has proposed embedding a network-on-chip...
Hardware accelerators (HwAcc) provide good performance in computation intensive applications. Integrating hardware accelerators in a cloud environment is the optimal way to improve the quality of service. However, mapping all possible application statically into the reconfigurable fabric of the FPGA is rather impractical and prohibitively expensive in terms of resource and power consumption. This...
The Stratix 10 project started with aggressive performance, size, and feature goals, all to be met on a lean schedule. Meeting these performance goals led to a restructuring of the entire configurable clock system into a regular gridded network, which subdivided the device into a composable system of "sectors". Sectors aligned with the needs of the project schedule, since they allowed complexity...
This paper presents a reconfigurable and adaptive routable Network-on-Chip (NoC) called RAR-NoC, which can be adapted at runtime to the application requirements. Therefore, RAR-NoC supports runtime reconfiguration of the routers as well as dynamic selection of the routing algorithm (XY or West-First) for each message. To evaluate the benefits of this flexible architecture, a heterogeneous reconfigurable...
This paper presents a memory hierarchy with the support of network-on-chip (NoC) for MPSoC systems. The memory hierarchy consists of a shared global memory and private local memories. Each core in the system is equipped with two local memories, one for instructions and one for data. Those local memories are connected through a NoC for efficient data communication. We tested two different settings...
Modern computing systems for vision have to support advanced image applications. They involve several heterogeneous pixel streams and they have to respect hard timing and area constraints. To face those challenges, an adaptable ring-based interconnection network-on-chip (NoC) has been recently proposed. This NoC is based on a new router architecture, with a dynamically adaptable internal datapath,...
This paper presents a novel approach for a memory, which supports the flexibility of an FPGA-based dynamic reconfigurable System-on-Chip consisting of heterogeneous data processing nodes. The memory is accessible via the Network-on-Chip (NoC) and provides a dynamic mapping of address space for the different clients within the network. Different data transfer modes support especially the image processing...
This article presents the design of RecoNoC: a compact, highly flexible FPGA-based network-on-chip (NoC), that can be easily adapted for various experiments. In this work, we enhanced this NoC with dynamically reconfigurable shortcuts. These can be used to alter the NoC's topology to adapt to the system's communication needs. The design has been implemented and tested on a Xilinx Virtex-2 Pro FPGA,...
The presented work deals with reconfigurable systems with Self Adaptivity based on the FPGA technology. The work is based on partial dynamic reconfiguration of FPGA devices and analyzes Self Adaptive systems, their elements and features. The main part introduces placement algorithms and Step Adaptive algorithm for improving mapping on running network. The tests of algorithm are done on the sets of...
Recognizing the strategic importance of embedded computing for industry and society, the European Commission formed, together with industry, academia, and national governments, the European technology platform ARTEMIS (Advanced Research and Technology for Embedded Intelligence and Systems) in 2004. It is one goal of ARTEMIS to develop a cross-domain embedded system architecture, supported by design...
Networks-on-chip have a relative area and delay overhead compared to buses. These can be improved in application specific systems where heterogeneous communication infrastructures provide high bandwidth in a localized fashion and reduce underutilized resources. However, for general purpose architectures, design time techniques are not efficient. One approach for improving area and/or performance of...
Due to the advancement of VLSI (Very Large Scale Integrated Circuits) technologies, we can put more cores on a chip, resulting in the emergence of a multicore embedded system. This also brings great challenges to the traditional parallel processing as to how we can improve the performance of the system with increased number of cores. In this paper, we meet the new challenges using a novel approach...
The heterogeneous nature of the modern day applications has resulted in widespread use of Multicore SoC architectures. The emerging Network-On-Chip (NoC) interconnect architecture provides an energy-efficient and scalable communication solution for multiple cores, serving as a powerful replacement for traditional bus architectures. The key to the successful realization of such architectures is a flexible,...
With an increasing trend to implement Network-on-Chip (NoC)-based Multi-Processor Systems-on-Chips (MPSoCs), NoCs need to have guaranteed services and be dynamically reconfigurable. Many current NoCs consume too much area and cannot support dynamic reconfiguration. In this paper, we present an area-efficient Spatial Division Multiplexing (SDM)-based NoC. We replaced area consuming 32-bit to M-bit...
The implementation of a high-performance network-on-chip (NoC) requires an efficient design of the network interface (NI) unit that connects the switched network to the IP cores. In this paper, we present a two novel pipelined NI architecture between IPs and router of NOC. These network interfaces allow system designers to send data from IPs to NOC, and vice versa with low latency. We present how...
The use of dynamically and partially reconfigurable resources permits to support complex applications. If dynamic and partial reconfiguration offers new possibilities for applicative implementations, it could also provide new ways to design efficient interconnection architectures. In this way, R2NoC, a Network on Chip constituted of dynamically reconfigurable routers is presented. First characterizations...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.