The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper characterizes the scaling of maximum frequency in lower-performance and higher-performance field-programmable gate-array (FPGA) chips as a function of circuit size and complexity. The evaluation is based on synthesizing mesh and toroid circuit topologies with parameterized node count and interconnect width. Each node accepts two input bit vectors and generates two output bit vectors, and...
Compressors form the basic element of arithmetic circuits that are dominated by multi-operand addition operations. Compressor circuits based on carry-save logic have been used in past to realize parallel multipliers for ASIC implementation, however, owing to the peculiar architecture of FPGAs, these circuits do not map well on these platforms. In this paper, FPGA implementation of 4:2 compressor circuit...
We propose the first hardware implementation of standard arithmetic operators - addition, multiplication, and division - that utilises constant compute resource but allows numerical precision to be adjusted arbitrarily at run-time. Traditionally, precision must be set at design-time so that addition and multiplication, which calculate the least significant digit (LSD) of their results first, and division,...
In this paper, brief explanation will be given about system that can localize sound source based on FPGA, this system use five microphones with predefined distance, which will be used to acquire the Time Delay of Arrival (TDOA) data. TDOA is the parameter needed by sound source to arrive at corresponding microphone. The focus in this paper is providing high accuracy 3D sound source localization with...
Most modern FPGAs have very optimised carry logic for efficient implementations of ripple carry adders (RCA). Some FPGAs also have a six input look up table (LUT) per cell, whereof two inputs are used during normal addition. In this paper we present an architecture that compresses the carry chain length to N/2 in recent Xilinx FPGA, by utilising the LUTs better. This carry compression was implemented...
This paper describes digit-by-digit integer restoring and non-restoring algorithms for computing the cube root of a 33-bit radicand and gives improved methods for the implementations of the algorithms to speed up the computations. The methods include calculating multiplication products in advance with additions and using carry save adders (CSAs) to calculate the partial remainder at each iteration...
In this paper a work can be proposed in order to deliver that the Multiple constant Multiplication method is effective when we design an FIR Filter with direct form architecture with the possibility that it can become programmable transpose form Architecture and it configures into block FIR filter for the area and delay comprehension of many order FIR filters for both fixed and Rearranged the Blocks...
This paper describes the architecture and implementation, from both the standpoint of target applications as well as circuit design, of an FPGA DSP Block that can efficiently support both fixed and single precision (SP) floating-point (FP) arithmetic. Most contemporary FPGAs embed DSP blocks that provide simple multiply-add-based fixed-point arithmetic cores. Current FP arithmetic FPGA solutions make...
Proper closed loop has been an ever burning issue in many automotive industries. The industrial equipments which are governed by PID controllers have simple control structure and efficiency but still they suffer from large power consumption and slow mathematical computation. Many researchers have tried and are trying to design a low power, delay less PID. This paper reviews three MAC architectures...
Runtime reconfigurable systems become more prevalent in numerous practical applications because these systems have a great flexibility. This paper presents a reconfigurable system implemented on Xilinx Field Programmable Gate Array (FPGA) where partial bitstream relocation (PBR), configuration memory readback and internal registers restoration techniques are supported. It can reduce a number of partial...
An antilog is the inverse function of a logarithm. Today, conventional use of the term “antilog” has been replaced in mathematics by the term “exponent”. The binary logarithm is often used in the field of computer science and information theory because it is closely connected to the binary numeral system, in the analysis of algorithms and Single-elimination tournaments etc. So an efficient system...
The use of floating point unit has lot of application in real time embedded systems. Algorithms like fast fourier transform(FFT) from the digital signal processing (DSP) domain often make extensive use of floating-point arithmetic. This paper presents the design and implementation of an efficient single precision floating-point processor in FPGA. This processor can be dynamically configured, loaded,...
Reconfigurable computing for DSP remains an active area of research as the need for integration with more traditional DSP technologies become apparent. Traditionally, most of the work in the field of reconfigurable computing was focused on fine-grained FPGA devices. Over the years, the focus was shifted from bit level granularity to a more coarse grained composition. In this paper, we present the...
Pairings such as Tate, Ate and Optimal-ate are used to perform operations over special form of elliptic curves known as Barreto-Naehrig (BN) curves. Computation of the pairings involve the floating point operations which is difficult to perform and for this purpose special hardware blocks are used. Existing techniques uses Montgomery multiplication algorithm which uses one hardware block corresponding...
This paper provides a new design methodology to improve the efficiency of a parallel dual core cryptoprocessor for computing pairings over Barreto Naehrig (BN) curves. The proposed design is specifically optimized for Field Programmable Gate Array Platforms(FPGA). We explore the inbuilt features of an FPGA device to improve the efficiency of a cryptoprocessor for computing 128-bit secure pairings.
This paper presents a streaming processor specifically designed for adaptronic and biomedical engineering applications. The main characteristics of the streaming processor are the flexibility to implement floating-point-based scientific computations commonly performed in the digital signal processing application. The floating-point operators are connected to dual-port memories through separated 3...
Large multiplication is widely used in modern cryptography systems, multimedia and signal processing applications. This paper presents three pipelined large multiplier (PLM) design methods that use specialized multiplier logic provided in modern FPGA platforms. The presented design methods provide efficient usage of symmetric multiplier resources. Also, they can be used to map a large multiplier even...
This paper addresses the direct optimization of pipelined adder graphs (PAGs) for high speed multiple constant multiplication (MCM). The optimization opportunities are described and a definition of the pipelined multiple constant multiplication (PMCM) problem is given. It is shown that the PMCM problem is a generalization of the MCM problem with limited adder depth (AD). A novel algorithm to solve...
When the multi-channel FIR filter is implemented in FPGA, the demands for resources are to be reduced. The paper optimized the structure of multi-channel FIR filter whose multi-channel input data are transported through time-multiplexed mechanism. In the optimized structure of multi-channel FIR filter which is implemented in FPGA the multi-channel input data share the same single-channel FIR filter...
A method for generating high speed FIR filters with low complexity for FPGAs is presented. The realization is split into two parts. First, an adder graph is obtained using an existing multiple constant multiplication (MCM) algorithm. This adder graph describes the required multiplier block of the FIR filter using only additions/subtractions and shifts. Secondly, a novel FPGA-specific combined schedule...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.