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This paper presents an efficient design of a processor-based PDP timing controller that supports multiple high frequency control signal channels in multi-clock domain. We implemented a prototype system using the proposed design on FPGA attached to 42-inch and 50-inch PDP panels with HD resolution.
This paper proposes Flex Core, a hybrid processor architecture where an on-chip reconfigurable fabric (FPGA) is tightly coupled with the main processing core. Flex Core provides an efficient platform that can support a broad range of run-time monitoring and bookkeeping techniques. Unlike using custom hardware, which is more efficient but often extremely difficult and expensive to incorporate into...
We propose a minimalistic processor architecture tailoring Wave Field Synthesis (WFS)-based audio applications to configurable hardware. Eleven high-level instructions provide the required flexibility for embedded WFS customization. We describe the implementation of the proposed instructions and apply them to a multi-core reconfigurable WFS architecture. Our approach combines software programming...
New tendencies envisage multi-core as a promising solution for real-time application. And the key challenge is how to improve the communication efficiency. In this paper, we propose a new multi-core architecture, which adopts the hybrid interconnection composed of both bus-based and NoC architecture, and we also introduce several technologies to improve its communication efficiency. Adopting the new...
This paper presents a demonstration on various grayscale and binary processing operations performed in real-time on the MIPA4k array processor prototype system. The emphasis of the demonstration is on asynchronous wave propagation operations in both grayscale and binary domains and a related object segmentation and tracking algorithm discussed. However, also the functionalities proposed in the other...
Smart Grid and Smart Meter initiatives seek to enable energy providers and consumers to intelligently manage their energy needs through real-time monitoring, analysis, and control. We have developed an inexpensive FPGA implementation of a spectral envelope preprocessor. This FPGA permits cost-effective and richly detailed power consumption monitoring for individual loads or collections of loads. It...
A kind of image processing with a low power dynamically reconfigurable processor array (DRPA) prototype MuCCRA-3 implemented with 65 nm CMOS process will be shown. The measured power is also exhibited during execution, and compared with Xilinx Virtex-5 FPGA using exactly the same environment. The demonstration shows that more than 10 times better power efficient computation is achieved using MuCCRA-3...
While the computational core is becoming faster and faster, the communication efficiency between the processors has become a bottleneck which limits the performance of multiprocessor system-on-chip (MPSoC). This paper focuses on design and implementation of AXI bus protocol-based MPSoC architecture. Firstly, the RTL models of 4 NIOS II processors using AXI communication architecture are developed...
The reconfigurable mesh model for massively parallel computing has recently been rediscovered and proposed as the basis of a practical many-core architecture. With this paper, we are the first to study the power and energy requirements of reconfigurable meshes. We present two methods to reduce the power consumption, exploiting characteristics of typical reconfigurable mesh algorithms. We extend our...
Modern network devices employ deep packet inspection to enable sophisticated services such as intrusion detection, traffic shaping, and load balancing. At the heart of such services is a signature matching engine that must match packet payloads to multiple signatures at line rates. However, the recent transition to complex regular-expression based signatures coupled with ever-increasing network speeds...
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