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While efficient simulators for Time-Multiplexing Cellular Neural Networks have been reported, no reports on implementations in FPGA have been presented. A Time-Multiplexing Cellular Neural Network is implemented within a FPGA for image processing. The network has been used to perform tasks, such as edge detection and noise remover over several test templates. Implementation results are compared with...
A 2-D Cellular Neural Network structure with space invariant neural weights is widely used in image processing applications. Recent advances VLSI technology appears to be very promising to use discrete time CNNs for real time vision applications. In this paper, a system-on-chip implementation which consists of a new CNN emulator design and a processor which performs template learning algorithm is...
This paper presents a Field Programmable Gate Array (FPGA) based implementation of the Fourier Segmentation process that is used in the Empirical Wavelet Transform. The Empirical Wavelet Transform is a method to determine the modes of a given signal by building wavelets that are adapted to the processed signal. Such wavelets are constructed by determining the location of the information in the spectrum...
This paper presents a non-uniform sampling analog-to-digital converter (ADC) architecture using an adaptive level-crossing technique. The architecture can be dynamically configured through three parameters that allow the user to match the ADC to the signal to be acquired or to application constraints. When applied to sparse signals, this architecture outperforms uniform sampling architectures. In...
Road Sign Detection (RSD) is becoming a major goal of the safety Advanced Driving Assistance Systems (ADAS). Automotive research area share many publications based various techniques used to detect and classify signs. This paper provides a hardware detection-based correlation architecture using Xilinx System Generator (XSG). This proposed architecture outsets with pre-processing step: RGB to YCrCb...
In this project, reconfigurable hardware architecture is used for performing the polynomial matrix multiplications (PMM). Hardware architecture is designed by using the Xilinx system generator tool. System generator enables the use of the math works model-based Simulink design environment for FPGA design. For designing PMM system, Fast Fourier Transform (FFT) technique is used rather than Convolution...
Multifunction parallel image processing systems use standard buses to do inter core communication. Faster and scalable approaches are needed to improve the throughput of the system, but for data heavy applications like Image Processing (IP) algorithms there is a need for constant data transfer between different functional blocks on chip. The solution would either be hardwired buses or controlled communication...
Proportional Integral Derivative (PID) Controller is most well-known and consistent with industry. It is applied to many applications such as flow, temperature, motor control, robotic applications, biomedical applications, etc. Many applications demands fast response. Parallel implementation of proportional, integral, derivative action accelerates its response which can be achieved by using field...
In this paper, we have investigated pipeline and parallel processing architectures of finite impulse response (FIR) filter for efficient field programmable gate array (FPGA) implementation. Our simulation results shows that parallel processing architecture is more efficient as compared to pipeline architecture. Further, it is shown that fast FIR architecture is most suitable as compared to conventional...
QR decomposition has been widely used in many signal processing applications to solve linear inverse problems. However, QR decomposition is considered a computationally expensive process, and its sequential implementations fail to meet the requirements of many time-sensitive applications. The Householder transformation and the Givens rotation are the most popular techniques to conduct QR decomposition...
This paper aims the hardware co-simulation of parameterized Walsh code with classical counter architecture using MATLAB SIMULINK based Xilinx System Generator software tools. This is an implementation of the theory which replaces a general Sine and cosine function by set of orthogonal functions such as Rademacher functions and Walsh functions. We investigate 64-orthogonal set for 3G standard such...
With latest advancements in architecture, reprogram ability and availability of abundant on-chip resources, FPGAs (Field Programmable Gate Array) are used as hardware accelerators to speedup computationally intensive tasks with inherent parallelism. However non-availability of standard MATLAB and C/C++ computation routines and communication interface for general purpose programming restricted researchers...
This paper focused on the design of 32 bit IEEE 754 single precision floating point architecture for 8 point FFT. The total design is in combinational form. The FFT design is simulated in Active HDL. Results are verified with MATLAB simulation. Correctness is obtained up to twenty two bit. The design is tested for complex input data (separately for real and imaginary data). For low power design pipelining...
Design and evaluation of a CORDIC (COordinate Rotation DIgital Computer) algorithm for a floating-point division operation is presented in this paper. In general, division operation based on CORDIC algorithm has a limitation in term of the range of inputs that can be processed by the CORDIC machine to give proper convergence and precise division operation result. A hardware architecture of CORDIC...
This paper presents a prototype of a high-throughput 4 × 4 64-QAM MIMO receiver consisting of a channel matrix QR decomposition, a soft-output K-Best MIMO detector and a Convolutional Turbo Code decoder. The proposed MIMO receiver provides low processing latency and a pipelined architecture scalable to a larger number of antennas and constellation order. Therefore, it is suitable for LTE-Advanced...
This paper presents a digital system architecture for a two-input one-output zero order ANFIS (Adaptive Neuro-Fuzzy Inference System) and its implementation on an FPGA (Field Programmable Gate Array) using VHDL (VHSIC Hardware Description Language). The designed system is used for nonlinear function generation. First, a nonlinear function is chosen and off-line training is carried out using MATLAB...
Since decades, fractional Fourier transform has taken a considerable attention for various applications in signal and image processing domain. On the evolution of fractional Fourier transform and its discrete form, the real time computation of discrete fractional Fourier transform is essential in those applications. On this context, we have proposed new hardware architecture for implementing a Discrete...
Software Radio is a burgeoning application in the domain of wireless communications. A lot of effort has recently been directed into developing practical algorithms for IF based, multi-standard Software Radio receiver architectures. Significant issues exist in developing an efficient implementation suitable for the processing of multiple standards through a single architecture with the help of sample...
A software defined radio (SDR) is a device in which the functionality can be altered with the help of software. Hence defining the difference in behavior for various technologies in software, removes the need for hardware alterations during a technology upgrade. The role of modulation techniques in an SDR is very crucial since modulation techniques define the core part for any wireless technology...
The sequential behavior of general purpose processors presents limitations in applications that require high processing speeds. One of the advantages of FPGAs implementations is the parallel process capability, allowing acceleration of complex algorithms. Nowadays it is common to find FPGA implementations in applications requiring high speed processing. In this paper a hardware architecture for computing...
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