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Routing algorithms can improve network performance by maximizing routing adaptiveness but can be problematic in the presence of endpoint congestion. Tree-saturation is a well-known behavior caused by endpoint congestion. Adaptive routing can, however, spread the congestion and result in thick branches of the congestion tree — creating Head-of-Line (HoL) blocking and degrading performance. In this...
The Network on-Chip (NoC) is considered as an emerging technology for distributed embedded systems which is proposed as an alternative interconnection solution in Mutli-Processors System on-Chip (MPSoC). This paper proposes a graphical toll that allows researchers to generate and configure quickly their Network on-Chip in the hope to evaluate easily their contributions in no time. Unlike major existing...
A simple network model with torus topology and the virtual cut-through routing have been considered in order to find out and analyze certain relationships that can be used as a starting point for a deeper theoretical analysis and further research. An expression for the saturation point (message generation rate at which network saturates) and approximate expressions for the latency as a function of...
Big Data concerns processing of large volumes of digital data with high velocity and variety. Big Data technologies allow the analysis of data in real time, which is critical for various eScience applications. In order to meet the growing demand of Big Data applications, the infrastructures must be flexible enough to adapt to the characteristics of the applications. Most of the solutions presented...
In today's datacenters, there is an increasing demand for more network traffic capacity. The majority of the increase in traffic is internal to the datacenter, i.e., it flows between different servers within the datacenter. This category of traffic is often referred to as east-west traffic and traditional hierarchical architectures are not well equipped to handle this type of traffic. Instead, they...
Designing low-latency network topologies of switches is a key objective for next-generation large-scale clusters. Low latency is preconditioned on low hop counts, but existing network topologies have hop counts much larger than theoretical lower bounds. To alleviate this problem, we propose building network topologies based on uni-directional graphs that are known to have hop counts close to theoretical...
Network-on-Chip (NoC) is a nascent approach for reducing the communication bottleneck of multicore System-on-Chip (SoC). As the number of cores are increasing on SoC due to high performance demand of the consumer electronics and processing systems like servers, the low power and low latency NoC is required. Topologies are one of the most important parts of a NoC design, with considering the performance...
System-Level simulator is proposed to determine the ability of synchronous and asynchronous NoCs to alleviate the process variation effect. Throughput variation and different delay components variation are provided by the newly developed framework. System-Level simulation shows similarities with circuit-level simulation in terms of behavior and performance variation trend when moving from one technology...
Today's data center topologies mostly comprise multi-rooted trees with many equal-cost paths between the (source, destination) node pairs. Equal Cost Multi-Path (ECMP) forwarding is extensively used to leverage the multipath diversity in data center networks. However, ECMP forwarding might reduce the overall throughput significantly because of the random hash collision between multiple large flows...
Future applications will require processors with many cores communicating through a regular interconnection network. As the semiconductor industry advances to the deep sub-micron and nano technology points, the on-chip components are more prone to the defects during manufacturing and faults during system life time. In order to ensure the reliability of network-on-chip (NoC) under the faulty circumstance,...
Nowadays, SoC uses Network on Chip (NoC) to connect its increasing number of building blocks. FPGAs, like SoCs, can use NoC to connect its increasing number of tiles, memories, DSP slices and embedded processors. But one drawback of using NoC is that increasing its router ports will affect the area, power and frequency of the system significantly. For FPGAs to benefit from the NoC approach we have...
In High-Performance Computing (HPC) systems, the design of the interconnection network is crucial. Indeed, the network topology, the switch architecture and the routing scheme determine the network performance and ultimately the system one. As the number of endnodes in HPC systems grows, and the supported applications become increasingly demanding for communication, the use of techniques to deal with...
The success of the Internet around the world has produced many benefits, but due to IP protocol stack limitations, the IP addresses exhaustion problem soon arose. Although it has been proposed several solutions to alleviate it, the problem still remains, specially in the emerging countries, which have a reduced pool of public IPv4 addresses. Classless Inter-Domain Routing (CIDR) scheme has partially...
In Many/Multi-core processor architectures, hundreds and thousands of Intellectual Property (IP) cores are integrated to reinforce parallel processing and high performance computing. Integration of IP cores is effectively realized by a scalable communication framework, Network on Chip (NoC). NoC comprises of routers and interconnection links which aid transfer of information between IP cores. It is...
As the scale of parallel computer systems becomes larger year by year, interconnection networks with low node degree and short diameter are required for achieving high communication performance at low cost. This paper presents a general alternative to hypercubes, named KMS-Cube, that keeps interesting topological properties of the hypercube but has a low node degree. A KMS-Cube, denoted by KMSC(k,...
Network on Chip (NoC) has emerged as an interconnection solution for the modern digital systems, especially for System on Chip (SoC), due to the large number of IPs in the system that need to communicate. Various systems and routers have been introduced; hence the need to make a reusable verification environment to test both single routers and networks. In this paper, we propose a reusable verification...
This work introduces the notion of multiple virtual logical networks on a single hardware NoC. It details how it can be implemented and describes the meta-routing mechanism used within. We define a virtual logical network as a network in which the neighborhood is not determined by physical locations in the physical topology. A node can conceptually be a neighbor of any other node even if physically...
In recent years, there has been a dramatic increase in utilization of FPGAs to enhance the speed-performance of many real-time compute and data intensive applications on embedded platforms. FPGA-based designs leverage parallelism in computations to achieve high speed-performance. Parallel computations require multi-ported memories to provide any number of ports for simultaneous multiple read/write...
Due to the centralized control, network-wide monitoring and flow-level scheduling of Software-Defined-Networking (SDN), it can be utilized to achieve Quality of Service (QoS) for cloud applications and services, such as voice over IP, video conference and online games, etc. However, most existing approaches stay at the QoS framework design and test level, while few works focus on studying the basic...
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