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Network on Chip system establishes better on-chip communication for a chip multiprocessor system than the traditional bus based system. In the network design, the selection of routing algorithm and the network topology play a vital role in the performance of on-chip interconnects. One of the problems in routing is congestion of traffic which hampers the performance of the system to a great degree...
Network-on-Chip (NoC) has been proposed as a solution for the communication challenges of Multi-Processor System-on-chip (MPSoC) design in nanoscale technologies and it has better reusability and scalability. However along with the advantages of any communication parameter follow its disadvantages. Most state-of-the-art NoC architecture and their design flows is optimized for a single application,...
The efficiency of a router in a Network on Chip (NoC) is characterised by good performance, minimum packet latency, area and power. In this paper, we propose an adaptive deflection router for mesh NoC which offers higher speed of operation by reducing the router critical path latency. We propose a single cycle router that uses an intelligent decision making logic to store deflected flits in minimum...
This paper presents a novel method to deal with deadlocking in multicast routing in mesh Network-on-Chip. The proposed design does not use the virtual channels used in the conventional designs, instead it provides a unique method to interleave data from different input ports. The method avoids deadlocking in tree-based multicasting by providing a flit-by-flit interleaving and at the same time reducing...
With the rapid increase in the number of processor cores on a chip, packet-switching networks on chip (NoCs) have emerged as a promising paradigm for designing scalable communication infrastructures for future multi-core processors. The quest for high-performance networks, however, has led to very area-consuming and complex routers with marginal return in performance. On the other hand, studies show...
In this paper, a novel mesh based architecture named as Central Switch Noded Mesh architecture (CSNM) with Switching Nodes (SWN) placedat the center of each square block of mesh topology is proposed. The SWNs form a subnetwork inside the actual mesh network and examines the global traffic and informs the router as it routes its packets adaptively. We have also defined an adaptive routing algorithm...
Network on Chips (NoCs) has now replaced the bus based architectures for communication between different cores in a multiprocessor System on Chip (SoC). NoC integrates SoCs in a better manner. It has the advantage of good scalability and high bandwidth. The communication on NoC is carried out by means of routers. Routers are the back bone of NoC. The design of routers is different for different topologies...
Network on Chip (NoC) is a new paradigm to make the interconnections inside a System on Chip (SoC). By the developments achieved in integrated circuits (IC) manufacturing there have been attempts to design vast amounts of network on the chips in order to achieve more efficient and optimized chips. A better routing algorithm can enhance the performance of NoC. XY routing algorithm is a distributed...
Asynchronous NoC switch is proposed as a robust design to mitigate the impact of process variation. Circuit analysis is used to evaluate the influence of process variation on both synchronous and asynchronous designs. The delay and throughput variation are evaluated with different technologies. Although the asynchronous switch has large delay variation as compared to synchronous switch, high throughput...
In Network-on-chip design two of the most important performance indices are the average delay of packets and power dissipation. The first depends on the level of congestion of the communication system, the second is strongly influenced by the power dissipated by the links of a network-on-chip (NoC) which accounts for a significant fraction of the overall power dissipated by the on-chip communication...
With the technological advancements a large number of devices can be integrated into a single chip. So the communication between these devices becomes vital. The network on chip (NoC) is a technology used for such communication. A router is the fundamental component of a NoC. This paper focuses on the implementation and the verification of a five port router. The building blocks of the router are...
Multiprocessor System-On-Chips (MPSoCs) is an emerging technology. They provide support to the design complexity of embedded systems. MPSoCs will combine several types of processor cores and data memory units of widely different sizes, leading to a very heterogeneous architecture. As the feature size is continuously decreasing and integration density is increasing, interconnections have become a dominating...
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