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In Many/Multi-core processor architectures, hundreds and thousands of Intellectual Property (IP) cores are integrated to reinforce parallel processing and high performance computing. Integration of IP cores is effectively realized by a scalable communication framework, Network on Chip (NoC). NoC comprises of routers and interconnection links which aid transfer of information between IP cores. It is...
We can enhance the performance and efficiency of deflection-routed FPGA overlay NoCs by exploiting the cascading featureof the Xilinx UltraScale BlockRAMs. This allows us to (1) hardenthe multiplexers in the NoC switch crossbars, and (2) efficientlyadd buffering support to deflection-routing. While buffering isnot required for correct operation of a deflection routed NoC, it can boost network throughputs...
Network-on-Chip (NoC) architecture provides a platform for inter-core communication in a multicore system. In this work we propose a single cycle minimally buffered Route-on-Fly (RoF) router that uses the link traversal time of the data packet to perform route calculations. We also propose a 2 cycle variant of the Route-on-Fly (RoF) router in this paper. 4 × 4 NoC meshes built using proposed architectures...
Router architecture plays an important role in a Network-on-chip design for achieving high throughput and low latency. In this paper, output buffer router has been emulated using the concept of Distributed Shared Buffer Router. Main focus of the design was to increase the throughput and lower the latency with minimum area and power overhead.
Networks-on-chip (NoCs) have become increasingly widespread in recent years due to the extensive integration of many components in modern multicore processors and SoC designs. One of the fundamental tradeoffs in NoC design is the radix of its constituent routers. While high-radix routers enable a richly connected and low diameter network, low-radix routers allow for a small silicon area. Since the...
Buffer resource minimization plays an important role to achieve power-efficient NoC designs. At the same time, advanced switching mechanisms like virtual cut-through (VCT) are appealing due to their inherited benefits (less network contention, higher throughput, and simpler broadcast implementations). Moreover, adaptive routing algorithms exploit the inherited bandwidth of the network providing higher...
The current Internet is suffering from IPv4 address depletion. Stateless NAT64 is proposed to facilitate the IPv4/IPv6 co-existence and transition. In the past, the stateless NAT64 is mainly for IPv6 clients to access both IPv6 and IPv4 servers. As the fast growth of IP address consuming Internet services, the support for pure IPv6 servers is becoming urgent. In this paper, we propose a design of...
Communication plays a crucial role in the design of high performance Multiprocessor Systems-on-Chip (MPSoC). Accordingly, Networks-on-Chip (NoC) have been successfully employed as a solution to deal with communication in complex MPSoCs. NoC-based architectures are characterized by various tradeoffs related to structural characteristics, performance specifications, and application demands. In new technologies,...
In the current Internet, IP address system suffers from the overloading of semantics. This brings great challenge to the scalability of the routing system and the mobility of network hosts. One proposal called Locator/ID separation which separates network layer into locater layer and ID layer has been discussed within the IETF and IRTF for years. In the meantime, the Internet is going through a phase...
In System on Chip, buses and point to point links are used as a communication infrastructure between one IP to another, but these cannot provide efficient interconnect from performance point of view. So NoC architecture was proposed to provide communication in multiprocessor SoC and overcome the limitations. This paper has implemented a 5-port 32-bit and 64-bit router architecture using wormhole routing...
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