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A novel modification to Z-Source DC circuit breakers has been proposed to reduce power consumption from its predecessor significantly. The power thyristor serves as the means of circuit isolation and voltage blocking in the event of a fault in traditional Z-Source DC circuit breakers. However, Z-Source circuit breakers direct full load current through the Thyristor. The resulting voltage difference...
Main goal of this paper is to propose a compact library of polymorphic gates based on suitable type of reconfigurable transistors. In fact, their exploitation brings a significant advantage for space-efficient synthesis of complex polymorphic circuits. Actual behaviour of those transistors closely depends on so called ambipolar property. That particular aspect simply allows the selection of n- or...
Simultaneous switching noise (SSN) occurs when clock synchronized core circuits switch simultaneously. Furthermore, a huge amount of the SSN generated by simultaneous switching current (SSC) with high power distribution network (PDN) impedance at anti-resonance can cause electromagnetic interference (EMI) problems and logic failure. In multi-core processors, the spectrum of SSC is varied by power...
A novel Impedance Generation Circuit is proposed in this paper and is also implemented. The need for this is the lack of availability of such a device in the market at an affordable price and also the versatility it provides. Decade boxes such as DRB, DCB or DLB use switching of the corresponding passive elements (R, C, L variations) whereas the device proposed in this paper uses only variations in...
The existence of parasitic capacitances surrounding switching devices has been well established in the field. These capacitances are capable of having significant impact on the analysis, design, and performance of switched mode power supplies through increased switching loss or altered converter dynamics in the soft-switched case. As power converters continue to move to higher frequency, these effects...
In this paper a new voltage buffer to realize high speed and low power dissipation switched-capacitor filters is proposed. The drain-follower achieves 300MHz bandwidth with 2pF load; DC gain of 0.993V/V, 1mV offset voltage, −60 dB total harmonic distortion at 0.4 VPP output voltage and 58.5µW power dissipation from 1.5V supply. A unity-gain buffer switched-capacitor biquad filter has been implemented...
An in-depth analysis is performed on the third-order intermodulation distortions (IMD3) in the switching pair of active CMOS mixers. The nonlinear time-varying switching pair is described by a hypothetical circuit composed of a nonlinear time-invariant circuit cascaded with a linear time-varying circuit. This allows us to apply power and Volterra series for nonlinearity analysis. The analysis reveals...
A high isolation and low insertion loss transmit/receive switch is presented. The T/R Switch is based on the TSMC 0.18 μm 1P6M RFCMOS process. Shunt inductor resonance and body-floating techniques are used to improve the isolation and power handling capability. The simulation exhibit the insertion loss is 612mdB, the isolation between transmitter and receiver is 44.3 dB, input 1-dB compression point...
Simultaneous switching noise (SSN, also called delta-I noise) has became a tremendous challenge to the reliable operation of high speed circuit. A new method for modeling SSN of gapped power-ground planes is proposed in this paper. The gapped power-ground planes characteristics are derived from a hybrid field-circuit method. With this method, the parallel power-ground planes resonance characteristics...
This paper investigates the estimation of the coupled simultaneous switching noise (SSN) induced from power delivery networks (PDNs) in memory test boards. When the signal changes its reference plane in the board, voltage fluctuation occurs that induces the SSN in the PDN. This induced SSN affects other signals in the test board, reducing signal quality and test reliability. To avoid this problem,...
The cellular mobile communication industry has recently been one of the fastest growing industries. This paper presents efficient techniques in the design of switching mode class E power amplifiers by reducing switching losses. A typical class E circuit has been design-optimized for 900 and 1800 MHz. Matching networks are used to reduce power consumption. The simulated results were analyzed in terms...
A novel methodology for accurate and efficient static timing analysis is presented in this paper. The methodology is based on finding a frequency domain model for the gates which allows uniform treatment of the gates and interconnects. It is shown that despite the highly nonlinear overall gate model, a frequency domain model of the gate with the model parameters, gate moments, as functions of the...
In this paper, the design of a compact planar bandpass filter above a defected ground plane is presented. The filter is designed as a combination of microstrip resonators and exploits the properties of a planar electromagnetic bandgap (EBG) structure patterned unto the ground plane of the printed circuit board material to provide a very wide stopband of up to 5 times the fundamental frequency. The...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
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