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This paper investigates the use of stacked depletion-mode n-channel MOSFET (D-MOS) for RF switch applications. Compared to the commonly used enhancement-mode MOSFET (E-MOS), the D-MOS transistor offers a significant reduction in on-state resistance (RON) and off-state capacitance (COFF) simultaneously and an excellent figure of merit (RonX Coff) of 134fs (roughly 3X improvement) can be achieved. With...
As technology scales into the nanometer regime ground bounce noise and noise immunity are becoming important metric of comparable importance to leakage current, active power, delay and area for the analysis and design of complex arithmetic logic circuits. In this paper, low leakage 1bit full adder cells are proposed for mobile applications with low ground bounce noise and a novel technique has been...
Gate-level timing simulation of combinational CMOS circuits is the foundation of a whole array of important EDA tools such as timing analysis and power-estimation, but the demand for higher simulation accuracy drastically increases the runtime complexity of the algorithms. Data-parallel accelerators such as Graphics Processing Units (GPUs) provide vast amounts of computing performance to tackle this...
An enhanced circuit model is developed for a 60-GHz single-pole single-throw (SPST) switch in 65nm CMOS technology in this paper. The enhanced circuit model involves the modeling of the drain-to-source parasitic capacitances that are introduced by the overlapped multi-finger drain-to-source metallization of the transistors and also the modeling the distributive and coupling effect of lines interconnection,...
Multiple Dynamic Supply Voltage (MDSV) is an attractive way to reduce dynamic power in Integrated Circuits. This technique introduces Level Shifter (LS) in order to commute from one voltage domain to another. Nevertheless, some LS inserted during the physical synthesis can degrade performance and power consumption, especially in specific power modes. In this work, we present a novel approach to dynamically...
Co-design of 60GHz wideband front-end IC with on-chip Tx/Rx switch in 65nm CMOS is presented. Passive macro-modeling (pmm) is utilized to convert S-parameter files from passive component EM simulations to state-space models in circuit netlist format which could be used in commercial SPICE simulator for various analyses without convergence issues. The co-design of on-chip switch and LNA/PA could achieve...
In this paper, a new logic style named as MOS current mode logic with feedback is proposed as an alternative to conventional MOS current mode logic for implementing digital circuits operating at high frequencies. The proposed circuit style employs a positive feedback that enhances the switching speed of the circuit. The use of feedback reduces the number of transistors needed to implement the circuit...
An improved CMOS large-signal model including the substrate/triple-well characteristics has been proposed for the application in high power-handling of CMOS RF switch circuit. In order to establish a NMOS transistor model in RF switch application, two types of test devices, series- and shunt-type NMOS transistors, have been designed and fabricated by using a standard CMOS 0.18 µm technology. Based...
This paper proposes a fast, precise transient response and frequency characteristics simulation method for switching converters. This method uses a behavioral simulation tool (MATLAB/Simulink) without using a SPICE-like analog simulator. The nonlinear operation of the circuit is considered, and the nonlinear function is realized by defining the formula based on the circuit operation and by applying...
This paper illustrates some design strategies for the design of mixed analog-digital integrated circuits in CMOS technology. In mixed-signal systems, crosstalk from switching logic gates can disturb the operation of analog circuitry. Therefore, it is necessary to take into account digital switching noise from early stages of design, by means of a suitable model. The analog designer should select the...
Based on the requirements of phase noise and frequency tuning range of the GSM system, this paper designs a voltage-controlled oscillator suitable for GSM/EDGE handset RFIC with the structure of no-tail current source and switched-capacitor array. The whole circuit uses TSMC 0.18 μm CMOS technology. The power supply is 3.3V. The simulation results show that the operating frequency covers 3296 ~ 3980...
A high isolation and low insertion loss transmit/receive switch is presented. The T/R Switch is based on the TSMC 0.18 μm 1P6M RFCMOS process. Shunt inductor resonance and body-floating techniques are used to improve the isolation and power handling capability. The simulation exhibit the insertion loss is 612mdB, the isolation between transmitter and receiver is 44.3 dB, input 1-dB compression point...
In earlier, Fault Analysis (FA) has been exploited for several aspects of analog and digital testing. These include, test development, Design for Test (DFT) schemes qualification, and fault grading. Higher quality fault analysis will reduce the number of defective chips that slip past the tests and end up in customer's systems. This is commonly referred to as defective parts per million (DPM) that...
For a high-speed and high-resolution current-steering D/A Converter (DAC), Spurious-Free dynamic range (SFDR) becomes a major limiting factor for its performance. This paper gives an overall analysis of its dynamic error due to non-ideal switching behavior and identifies the link between the 3rd or higher order harmonic distortion and digital encoding scheme for the first time so far as our knowledge...
While the lower power consumption of LC injection-locked frequency dividers (ILFDs) compared to digital dividers has made them increasingly attractive for use in frequency synthesizers, their narrow locking range remains an issue for the designers. One of the techniques to widen the locking range in these dividers is direct injection. In this paper, we present a simplified model of an LC ILFD and...
The paper presents a test calculation principle which serves for producing tests of switch-level logic faults in CMOS digital circuits. The considered fault model includes stuck-at-0/1 logic faults on the connecting control lines, as well as switch faults in the transistors. Both single and multiple faults are included. The transistor faults manifest themselves in stuck open (open circuit) and stuck...
The paper presents a test calculation principle which serves for producing tests of transistor-level faults in CMOS digital circuits. The considered fault model includes stuck-at-0/1 logic faults on the connecting control lines, as well as switch faults in the transistors. Both single and multiple faults are included. The transistor faults manifest themselves in stuck open (open circuit) and stuck...
This paper presents a miniature DC-70 GHz single-pole four-throw (SP4T) built in a low-cost 0.13-mum CMOS process. The switch is based on a series-shunt design with input and output matching circuits. Deep n-well (also called triple-well) CMOS transistors are used to minimize the substrate coupling. Also, deep trench isolation is used between the different ports to minimize the port-to-port coupling...
A VLSI switched capacitor signal processing circuit modeling method is presented. Such technique provides capability to effectively develop closed form signal transfer functions for various practical VLSI SC circuits. Application to the VLSI switched capacitor charge pump DC/DC converter circuit implementation demonstrated consistent results between the model and measurement of the fabricated circuit...
We analyze the carrier dynamics in MOSFETs under low voltage operation for a 90 nm CMOS technology. For this purpose the displacement (charging/discharging) current, induced during switching operations is studied experimentally and theoretically. It is found that the experimental transient characteristics can only be well reproduced in the circuit simulation of low voltage applications by considering...
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