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This paper presents an original multi-physics modeling methodology for the design and analysis of integrated crystal oscillators based on power-waves formulation. Conventional Barkhausen oscillation conditions criterion is derived in terms of reflection coefficients. Coupling module is introduced between the crystal resonator and the oscillator active-core in order to account for electromechanical...
Resonant rotary clocking is a next generation clocking technology for ultra-low power, multi-GHz range operation. Previous works demonstrate the feasibility of this technology with full-custom, low-complexity circuit implementations. In this work, the rotary operational principles are investigated at a larger scale, and physical design and timing verification methods are developed as a blueprint for...
This paper examines a new architecture that combines super regeneration and time-based signal processing concepts to implement frequency-to-time conversion. The proposed structure can also be used to perform LC-tank oscillators testing by using simple and low-resolution digital circuits. Its front-end consists of two cross-coupled oscillators, triggered in time by two step-like signals with a time...
This paper presents an efficient algorithm for post-synthesis logic simulation of digital circuits with oscillatory combinational loops. Oscillatory combinational loops can significantly degrade the performance of cycle accurate logic simulators. We provide an algorithm that first, dynamically detects oscillatory loops. Then, we introduce a novel approach to compute a multiple of their oscillation...
This paper presents the theoretical study of a monolithically integrated NEMS/CMOS oscillator with electrostatic actuation and piezoresistive detection. A feedback circuit based on a single active transistor is implemented. The proposed architecture is so compact that it can be implemented with ease in a sensor array application for example. A brief description of the NEMS resonator is given and the...
The high frequency of the rotary clocking technology is often susceptible to implementation parameters such as the variation in the total capacitive load distribution between the rings. SPICE simulations performed on the rotary rings with unbalanced capacitive load distribution show a 30.31% variation in the simulated frequencies across the rings. To address this problem, two novel methodologies called...
A digital-controlled oscillator (DCO) employing on-chip coplanar waveguide (CPW) resonator is proposed for 5 GHz-band wireless communication applications. A 10 bit DCO using on-chip designed, fabricated and tested. By comparing the measured results on the fabricated chip in 0.18 mum CMOS technology, it has noted that the proposed DCO employing on-chip CPW resonator is smaller in size and frequency-tuning...
In this contribution, a novel approach to exploring analog circuit behavior in the circuit's state space using visualization and multi-parallel particle simulation techniques is presented. Insights not acquirable by conventional circuit characterization methods can be obtained by combining different visualization aspects. The introduction of a visualized multi-parallel particle simulation allows to...
A new implementation of Chua's circuit employing unity-gain cells (UGC) as the active building blocks to emulate the behavior of the nonlinear resistor (NR) and the grounded inductor is introduced. The breakpoints and slopes associated to the NR as well as the numeric value of the inductor can be adjusted by the control resistors. The proposed circuit is suitable for implementation with the commercially...
This article presents a voltage-mode first-order all-pass filter based on merely single current controlled current differencing transconductance amplifiers (CCCDTA). The features of the circuit are that: the pole frequency can be electronically controlled via the input bias current: the circuit description is very simple, consisting of merely single CCCDTA and single capacitor, without any matching...
Hybrid CMOS-SET circuit architectures, which combine the merits of SET and CMOS devices, promise to be a more practical implementation for nanometer-scale circuit design. In this work we discuss and compare two popular hybrid CMOS-SET architectures - serial and parallel - in terms of power dissipation, drivability and temperature effects. We use MIB compact model for SET devices and BSIM3v3 Spectre...
Simultaneous switching noise (SSN) is an important issue for the design and test and actual ICs. In particular, SSN that originates from the internal logic circuitry becomes a serious problem as the speed and density of the internal circuit increase. In this paper, an on-chip monitor is proposed to detect potential logic errors in digital circuits due to the presence of SSN. This monitor checks the...
In this paper, a CMOS design of a network of relaxation oscillators is described. The parasitic gate-source capacitances of the MOS transistors are used to implement fast state variable of the relaxation oscillator. It is shown that circuit realization of the relaxation oscillators produces various dynamic behaviour. Simulations of the designed network show that the network produces autowaves.
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