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Convolutional Neural Networks are being studied to provide features such as real time image recognition. One of the key operations to support HW implementations of this type of network is the multiplication. Despite the high number of operations required by Convolutional Neural Networks, they became feasible in the past years due the high availability of computing power, present on devices such as...
Synthesis and implementation are two fundamental steps of the hardware design. Mountains of work in this area synthesize and implement your design from Hardware Description Language (HDL) description to the target FPGA device. We present ISE plus Customized P&R, a tool-chain converting Verilog designs into XDL that contains Xilinx FPGA implement modules. A key aspect of this tool-chain is that...
Underwater communication with autonomous underwater vehicles (AUVs) has strong demands on the modems caused by the constantly changing signal propagation (multi-path propagation, scattering, diffraction and refraction at thermal layers, etc.) of the underwater channel. These demands typically lead to a modem designed to match specific conditions. In this paper we present an automated model-based physical...
High level synthesis tools offered by either FPGA (Field Programmable Gate Array) vendors or from the public domain are evaluated in order to generate efficient and low complexity computational intelligence modules. This paper reports specific issues and comparative synthesis results in implementing basic modules of the FSVC classifier (Fast Support Vector Classifier) and cellular automata starting...
Traditional processor design approaches using CISC and RISC philosophies suffer from low performance. One of alternative approaches to improve system performance is instruction level parallelism (ILP). Among the processor architectures supporting ILP, very long instruction word (VLIW) processors offer some advantages such as low power consumption and hardware complexity. In this paper, we introduce...
The data transmission is fairly quick and easy in recent years. Nowadays, there are many serial data transmission methods, such as I2C, SPI, RS-232, USB (Universal Serial Bus), and so on. Recently, USB not only works with convenience but also transmits data fast. It becomes a standard peripheral interface between FPGA development board and personal computer (PC). To satisfy those requirements, the...
In the field of underwater acoustic communication, because of the signal transmission distance is shorter, generally uses the copper cable transmission. When the signal is needed to be transmitted in a long distance, its anti interference and attenuation will seriously affect the reliability of the transmission. Optical fiber transmits in higher speed and stronger antijamming. Its application is more...
Fractional interpolation is one of the most computationally intensive parts of High Efficiency Video Coding (HEVC). Therefore, in this paper, two pixel correlation based computation and energy reduction techniques for HEVC fractional interpolation are proposed. The proposed pixel equality based computation reduction (PECR) technique does not affect the PSNR and bit-rate. The proposed pixel similarity...
Heterogeneous computing with hardware accelerators is a promising direction to overcome the power and performance walls in traditional computing systems. CPU-accelerator integrated architectures, such as CPU with ASIC or FPGA based accelerators, are able to provide customized processing according to application requirements and are thus particularly attractive to speed up computation-intensive applications...
In recent years, synthetic test instruments have become increasingly popular in the automatic test equipment (ATE) market. This type of instrument gives users the ability to create custom solutions to better meet their test requirements. FPGA (Field Programmable Gate Array) based solutions are the most common synthetic test instrument on the market today. FPGA based solutions can work well due to...
The P4 language provides a way to describe a custom network packet processing behavior that involves header parsing, matching and assembling modified packets. Such abstraction represents a significant step towards removing the limitation of fixed-function networking devices. Our live demonstration shows a straightforward usage of an algorithm and tool that maps a P4 program to a general architecture...
Open source hardware projects are becoming more and more common. OpenRISC SOC, one of the prominent of these projects, has become quite popular with the support of volunteer developers. In this work, we have demonstrated the design of an DES (Data Encryption Standard) based system, that can be used in security applications, on ORPSoC-v2 (Openrisc Reference Platform System-on-Chip). Additionally, we...
BER (bit error rate) measurement is an important criterion to analyze digital communication systems. In literature this measurement generally performed through simulation programs like Matlab/Simulink. It is considered that the simulation programs may not represent a real communication system and also they are quite time consuming and expensive. However, modeling communication systems with parallel...
FPGAs have emerged as a cost-effective accelerator alternative in clouds and clusters. Programmability remains a challenge, however, with OpenCL being generally recognized as a likely part of the solution. In this work we seek to advance the use of OpenCL for HPC on FPGAs in two ways. The first is by examining a core HPC application, Molecular Dynamics. The second is by examining a fundamental design...
In this paper, we describe a Selectable Grained Reconfigurable Architecture (SGRA) in which each Configurable Logic Block can be configured to operate in either fine-grained or coarse-grained mode. Compared with the Mixed Grained Reconfigurable Architecture (MGRA), which has a fixed ratio of fine- and coarse-grained operation blocks and a heterogeneous floorplan, SGRA offers greater flexibility in...
This article shares experience and lessons learned in teaching course on programmable logic design at Universitas Muhammadiyah Surakarta, Indonesia. This course is part of bachelor of engineering (electrical) degree program. Project-based approach is chosen to strengthen these students' understanding and practical skills. Each year's project involves challenges for the students to solve by implementing...
Due to the proliferation of reprogrammable hardware, core designs built from modules drawn from a variety of sources execute with direct access to critical system resources. Expressing guarantees that such modules satisfy, in particular the dynamic conditions under which they release information about their unbounded streams of inputs, and automatically proving that they satisfy such guarantees, is...
Non-linear solar photovoltaic (SPV) system characteristics and its dependency on meteorological variables of irradiance and temperature; renders this energy source rather involved to visualize. In this paper a low power realtime SPV module simulator is realized in field programmable gate array (FPGA) XCS100E platform for classroom teaching. FPGA platform is used due to its parallel computing nature...
This article discusses the implementation of a wide band vectorial digital modulator and a tool to evaluate the Bit Error Rate. This modulator is capable of generate a wide band (up to 6.3 MHz) 16-QAM modulation in baseband. A second functionality programmed in the tool and reported in this article evaluates the Bit Error rate in order to measure the received signal quality. Results are validated...
With the invention of IoT, the image processing is reaching upto a distinct level as IoT is becoming a major part of every one life. These systems are creating many applications in image processing field such as image filtering and processing. The realization of this system was completed by means of a low cost ZedBoard Zynq 7000 FPGA and a Raspberry-pi. The output for the input image after processing...
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