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Although software engineers have high performance algorithms that could be implemented power-efficiently as embedded Systems on Chip (SoC) with modern FPGAs, there is still no easy path for them to a hardware realization, mainly due to the lack of appropriate design tools. We present an overview of a tool we have developed to boost the productivity of processor-centric SoC designs for FPGAs. Our tool...
System-on-Chip (SOC) design is an integration of multi million transistors in a single chip for alleviating time to market and reducing the cost of the design. Design reuse - the use of pre-designed and pre-verified cores is now the cornerstone of SOC design. It uses reusable Intellectual property (IP) blocks that supports plug and play integration and in turn allows huge chips to be designed at an...
A new method for performing Sparse Matrix-Vector Multiplication (SMVM) by using Network-on-Chip (NoC) architecture is described. In traditional IC design on-chip communications have been designed with dedicated point-to-point interconnections or shared-buses. Therefore, regular local data transfer is the major concern of many parallel implementations. However, when dealing with the parallel implementation...
In order to develop the core chip supporting binocular stereo displays for head-mounted display (HMD) and glasses-TV, a VLSI design scheme is proposed by using pipeline architecture for 3D display processing chip (HMD100B). Some key techniques including stereo display processing and high precision video scaling based on bicubic interpolation, and their hardware implementations are presented. A new...
SoC verification efforts involve multiple models of the design - RTL, FPGA, silicon and software models. With increasing design complexity, re-use of tests between models is a must. In this paper, we introduce a stimulus abstraction mechanism which greatly increases the re-usability of tests across models. We then demonstrate an implementation of the abstraction mechanism on two models of a PCI-express...
Today, designs of electronic systems are driven by application-specific embedded systems and system-on-chip (SoC). Designing these systems with conventional RTL-centric approach takes extremely long simulation cycles and painful verification process. The trend now is to describe these systems at a higher level of design abstraction. In this paper, we present a SystemC-based hardware/software (HW/SW)...
This paper proposes to introduce a programmable load/store unit (LSU) to C-based hardware design for an FPGA. The LSU provides flexible memory access methods that can hide memory access latency for hardware modules generated by a high-level synthesis tool. The hardware module with the LSU can treat efficiently not only simple streaming accesses but also sophisticated accesses such as image processing...
The demands for more powerful products and the huge capacity of today' s silicon technology move system-on-chip (SoC) designs from the leading-age to mainstream design practice. The one at the very top of the list of challenges to be solved for SoC design is verification. General agreement among many observers is that verification consumes at least 70 percent of whole design percent. SoC verification...
With the rapid development on the software-hardware co-verification of SoC, FPGA verification has become more and more critical for VLSI design, and it requires much more portion of time within the life circle of chip development. The time spent on the FPGA verification should be reduced to achieve a more efficient time-to-market for the IC product. Therefore, several strategies using both dynamic...
Several strategies that were employed for developing next-generation embedded Hard IP are reviewed. Mixed signal Hard IP developed for a multi-protocol serial interface physical layer at 0.622Gbps to 3.125Gbps was redeployed for 0.622Gbps to 6.375Gbps data rates. Ensuring quality meant adopting a strongly modular approach to design and verification. The configuration space of the Hard IP had to be...
Partial dynamic reconfigurability of modern FPGAs holds the potential of realizing autonomous and highly flexible systems-on-chip (SoC). Current devices can be configured with several partial bitfiles and replace particular ones on demand. But these precompiled bitfiles seriously lack flexibility: they are hardly relocatable and not adjustable. In other words, they are tied to their original functional...
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