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Reconfigurable Field Programmable Gate Arrays (rFPGAs) are employed extensively in spacecraft electronic systems to implement low-power adaptable systems that provide high density functionality. A challenge that must be tackled during system design is their high susceptibility to radiation induced Single Event Upsets (SEUs). A burst of energized particles may cause extensive damage to circuits. Even...
The following topics are dealt with: computer aided design; system estimation; system evaluation; design optimization; manufacturing-aware design; analog signal verification; mixed signal verification; process variation; digital system; embedded system; FPGA synthesis; power-sensitive condition; reliability analysis; memory system scheduling; physical synthesis; yield analysis; quality analysis; nanometer...
Energy efficiency and idle power consumption are becoming important parameters in the design of embedded systems that are realized with nanometer-scale CMOS devices. In nanometer-scale CMOS, Excessive quiescent power dissipation can lead to excessive heat generation and reliability issues. To address energy efficiency and idle power consumption, we present a novel Complementary Nano-Electro-Mechanical...
This paper presents a framework for the design space exploration of reliable FPGA systems based on a multi-objective genetic algorithm (NSGA-II). The framework takes into account several design metrics and outputs a set of Pareto-optimal design solutions. The framework is compared to the multi-objective version of simulated annealing (AMOSA) and it is empirically studied in terms of scalability using...
Increasing on-chip power densities with aggressive technology scaling has led to a low-power FPGA fabric with dual supply voltages. Such low-power techniques coupled with the heterogeneity of components on a FPGA have led to non-uniform aging of components due to temperature and voltage dependent failure mechanisms. In this paper, we present techniques in placement and routing stages of the design...
This paper proposes a novel fault tolerant algorithm for tolerating stuck-at-faults in digital circuits. We consider in this paper single stuck-at type faults, occurring either at a gate input or at a gate output. A stuck-at-fault may adversely affect on the functionality of the user implemented design. A novel fault tolerant design based on hardware redundancy (replication) is presented here for...
This paper presents a novel method to perform on-the-fly attestation of hardware structures loaded to reconfigurable devices. Given that a loadable hardware structure to a reconfigurable device is described by a binary bitstream, the hash value of this bitstream can be calculated to validate the hardware structure. To optimize this attestation, the hash value computation is implemented in hardware...
SRAM-based FPGAs are increasingly being used in space applications. However, there are still many concerns about the reliability of these devices in high-radiation environments, particularly due to the possibility of single-event upsets (SEUs) in the configuration memory. This paper presents an architecture for implementing radiation-hardened SoCs based on FPGAs. Previous works used triple module...
Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges when trying to maintain manufacturing yield rates and devices which will be reliable throughout their lifetime. New microarchitectures require new reliability-aware design methods that can face these challenges without...
The following topics are dealt with: IC reliability; low-power electronics; wireless systems; VLSI testing; DFT; CMOS design; IC simulation; circuit validation; FPGA; analog design; RFIC design; PLL design; signal integrity and DSM effects.
Field programmable gate arrays (FPGAs), particularly high-density, SRAM-based FPGAs, have vastly increased in features and capabilities to the point where they are a useful, low Non-Recurring Engineering (NRE) alternative to low-to-medium volume custom integrated circuit designs. In the aerospace field, however, they have been of limited use due to their high susceptibility to soft error upsets (SEUs)...
In this paper different variants of IIP realizations for SoC are given. It is described possible variants for practical usage in aerospace technology by designing FPGA projects. Several diversity-oriented SoC decisions are proposed. These decisions are considered for developing airplane IPS (ice protection system).
A self-sampling PI (proportional-integral) control all digital phase-locked loop (ADPLL) is introduced in this paper. Our design is based on the self-sampling PI control scheme. An advantage of this is that the transfer function as linear approximation of the system model remains almost the same at different lock point, a feature enabling theoretical analysis and systematic design. The complete design...
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