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CMOS power dissipation has multiple components: switching, short-circuit, and static. In order to be robust to power attacks, digital logic should eliminate the relation between processed data and each and every power component. Other sources of side-channel information are glitches and the early evaluation of signals. We improve over our previous work and propose a Look-Up Table (LUT) with increased...
This paper describes the technology-independent approach for FPGA (Field-programmable gate array) and ASIC (Application Specific Integrated Circuit) implementations. This approach is based on the reuse of portable building blocks described at RTL level, thus the design can be mapped to an ASIC or an FPGA devices with few RTL code changes when migrating between FPGA and ASIC. As case study, an OpenRISC...
This paper, deals with Latch Free Clock Gating technique for reduction of clock power and total power consumption in Low Power Arithmetic and Logic Unit and we have analysed power reduction on different FPGA devices. Without latch free clock gating technique in Low Power Arithmetic and Logic Unit the Contribution of Clock power was 39mW in Virtex-6 FPGA, 14mW in Virtex-5 FPGA, 24mW in Virtex-4 FPGA,...
Technical innovation drives the low power consumption requirements in ASIC design. This paper presents a SD card controller, in which two asynchronous units (BIU and CIU) are included for lower power structure. Adding low power mode to finite state machine makes this controller to shut down if no data or command is transferring for a long time. Only one FIFO is used to store temporary data in order...
Streaming applications describe a broad class of computing algorithms in areas such as signal processing, media coding and compression, cryptography, video analytics, network touting and packet processing and many others. For many of these applications, programmable logic devices such as FP-GAs are the implementation platform of choice due to their higher flexibility compared to ASICs and lower power...
In this work, we analyze the power requirement of synchronous and asynchronous VLSI circuit. There is 70.42% overall power reduction using asynchronous arithmetic circuit in place of synchronous circuits. In asynchronous, FDCE is used whereas FDRSE is used in synchronous. On 90nm Spartan-3 target device, we are taking counter as target design and arithmetic circuit is target design on 40nm Virtex-6...
The LSI design methodology against Differential Power Analysis (DPA) is important to realize a tamper-resistant cryptographic circuit. In order to verify the DPA resistance before ASIC fabrication, the DPA verification using FPGA is commonly used. However, power traces of ASIC differ from that of FPGA, so the DPA verification on FPGA cannot guarantee the DPA resistance on ASIC. On the other hand,...
The finite state machine (FSM) needed for the low power system pulse frequency modulated (PFM) mode in a buck converter is usually asynchronous because the fast clock needed for a synchronous FSM consumes too much power, or is maybe even not available. However, the implementation, verification and testing of a asynchronous FSM is complicated compared to an synchronous one. This paper presents a concept...
Power consumption has become the major factor that has to be considered while designing systems using reconfigurable devices, especially for battery-operated applications. Minimizing transitions is one of the ways to reduce power consumption. Overwriting a register with the same value occurs frequently in real digital systems. Such unneeded transitions increase the power consumption. To avoid this,...
Security at low cost is an important factor for cryptographic hardware implementations. Unfortunately, the security of cryptographic implementations is threatened by Side Channel Analysis (SCA). SCA attempts to discover the secret key of a device by exploiting implementation characteristics and bypassing the algorithm's mathematical security. Differential Power Analysis (DPA) is a type of SCA, which...
This paper presents a low power ultra-wide band digital receiver baseband architecture for handling IEEE 802.15.4a packets in real-time. Real-time processing allows duty cycling of the analog frontend, which is key to achieve low power consumption. The architecture consists of a programmable application specific instruction set processor and a set of application specific integrated circuits. The design...
Power optimization has become one of the most challenging design objectives of modern digital systems. Although FPGAs are more and more used, they are however still considered as power inefficient compared to standard-cell or full-custom technologies. New dedicated design approaches are thus needed to reduce this gap. In this paper, we address low-power design on FPGA through a dedicated High-Level...
Executing various combinations of external locating techniques provides many benefits over tracking and locating systems based on radar or GPS. These embedded radio positioning applications are built on a common set of functional capabilities. Development of a specific positioning system involves selection of a subset of these capabilities and implementation into a physical form that meets the size,...
Battery-powered sensor nodes call for low power consumption. As a crucial component, a power-efficient sensor network processor greatly reduce the overall power consumption of a node. In the paper, we propose a low-power asynchronous event-driven sensor network processor mapped onto an off-the-shelf clocked FPGA. Since the processor employs a bundled-data asynchronous encoding scheme, we define a...
In this paper, a novel technique, Input Change Detection (ICD) Circuit is proposed to reduce the dynamic power consumption of the Asynchronous Pipelined Systems with Bundled-Data Protocol. For every operand, a request pulse is given to the asynchronous pipelined system to process the operands, immaterial of whether the successive operands are same or different. This increases the dynamic power consumption...
This paper presents a flexible fully integrated self-calibrated quad-core 12-bit current-steering 180 nm CMOS DAC. Its novel architecture features multiple parallel sub-DAC unit cores. Their various combinations deliver smart flexibility in: performance, functionality, power management, design reuse, and smartness. The parallel sub-DAC units can be used together or separately to optimize the performance...
This paper presents an experimental evaluation on the feasibility of using an adaptive clock to enhance the performance of a Fast Fourier Transform (FFT). The FFT is implemented on an FPGA and results are simulated using commercial EDA tools. Dynamic power consumption and processing speed are compared to a standard FFT implementation using a fixed clock. Results show that using a dynamically variable...
According to the specified standard of airborne Photogrammetry, digital airborne cameras must have higher performance than ordinary civil cameras, which must shoot with shorter time interval and will generate huge data stream. In this paper, a digital airborne camera is designed and implemented in a single FPGA chip as a SOPC approach. The functions of image acquisition, storage and display are implemented...
This work proposes a new DPWM architecture that takes advantage of FPGA's advanced characteristics, especially the DLLs (Delay-Locked Loop) present in almost every FPGA. The proposed DPWM combines a synchronous (counter-based) block with an asynchronous block for increased resolution without unnecessarily increasing the clock frequency. The experimental results show an implementation in a low cost...
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