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In this paper, we design Tetris game which can rotate, generate randomly blocks, eliminate rows, and get scores based on FPGA. Multi-bit Flip-flops (MBFF) concept is implemented into a part of Tetris game to save power consumption and clock buffer area. The 2-bit MBFF and 4-bit MBFF technique are compared with the Single-Bit Flip-flop. Results show that Multi-bit Flip-flops technique is very effective...
Power and energy profiling of multi-core embedded SoC designs is a daunting task due to the lack of fine grain accurate and high sampling rate monitoring infrastructures. Furthermore, shared components used in common by multiple processing cores, make these designs difficult to analyze consumption of concurrent threads. FPGA development boards are currently used to implement multi-core SoC prototypes...
To mitigate the total power consumption in any circuit, ASICs or FPGAs, various conventional power gating techniques has been adopted depending upon the need of the application, dynamically controlled power gating procedure is one such power gating technique which can be used to reduce the total leakage power consumption of the circuit during the runtime. It can be applied on the real time application...
Run-time reconfigurable computing systems can offer increased flexibility when compared with traditional systems, a feature which can make them attractive for space-borne computing applications. This flexibility can allow a system to adapt to changes in operating conditions, such as reductions in available power, reductions in available resources (wither due to increases in task deployment, or due...
Achieving low power consumption, size reduction, and space optimization are all challenges in resource-constrained wireless devices such as Wireless Sensor Network (WSN) nodes. For instance, WSN nodes use duty cycle to improve their power efficiency, and wake-up radio (WUR) is used as a control channel to wake the nodes up. With its highly flexible features, a field-programmable gate array (FPGA)...
This paper presents a hardware implementation of morphological operations based on dynamic and partial reconfiguration (DPR) technique. This technique allows reconfiguring a part of the FPGA area with different functionalities at runtime. It is a promising solution toincrease performance in the system. Our design allows todesigner to choose the adequate morphological operation (erosion or dilation)...
Triple Modular redundancy technique is mostly used to mask transient faults in circuits operating in dependable systems. The generalization of this technique (known as nMR) allows the use of more than three redundant copies of the circuit to increase the reliability under multiple faults. The main drawback of nMR is its high power consumption, which usually implies in n times the power consumption...
Auto white balancing is the process of keeping the color of objects constant automatically under different illumination conditions by calculating a number of parameters from the image data. These parameters are used to change the image pixel values to keep the color constant. This paper discusses the Lam's auto white balance algorithm and presents a novel, high-performance and cost-effective implementation...
Power consumption in programmable devices has become a primary factor in design flow. Among the main concerns of power consumption, application performance, battery life, thermal challenges, or reliability, power consumption is crucial in FPGA designs for powered battery equipment. In this paper, we study the FPGA-based design for Sobel Edge Detection algorithm for low cost fall detector and we present...
This paper presents the power consumption analysis of two different routing architectures for mesh based FPGAs. The first architecture uses bidirectional Switch Box (SB) implemented using back-to-back tri-state drivers. The second one uses bidirectional SB implemented using tri-states and multiplexers. This paper highlights and experimentally demonstrates the benefit that can be reached by using multiplexers...
In this paper, we consider FPGA architecture optimization to reduce power consumption. We study two FPGA routing architectures. The first architecture uses bidirectional Switch Box (SB) implemented using back-to-back tri-state drivers. The second one uses bidirectional SB implemented using tri-states and multiplexors. Experimentation shows that when we use bidirectional SB based on tri-states and...
FPGA is considered to be a good platform for rapid prototyping of embedded designs. The power consumption is a growing problem with FPGAs, which is required to be optimized. In this paper, a method is proposed to estimate the dynamic power consumption of Micro Blaze based processing unit used in embedded designs for FPGA. The proposed method is based on experimental bench of implemented designs where...
Achieving low power consumption, size reduction, increased efficiency, and space optimization are all challenges in Wireless Sensor Networks (WSNs). WSNs use duty cycle to improve its power efficiency, and wake-up radio (WUR) is used as a control channel to wake up WSN nodes. With its highly flexible features, a field-programmable gate array (FPGA) is one of the attractive candidates for implementing...
Wireless sensor networks (WSNs) are networks of battery-powered sensing devices connected with wireless interfaces. Energy consumption and processing efficiency are relevant characteristics for these systems, thus energy-efficient architectures are required. Recent works show that FPGAs are suitable candidates for efficient data signal processing in WSNs. In this work, we evaluate Flash-based FPGA...
Content Addressable Memory (CAM) is a special memory that accomplishes search operation in a single clock cycle but CAM has disadvantages like low bit density and high cost per bit. In this paper, we present an implementation of a 512 x 36 SRAM-based TCAM (SR-TCAM) on a Virtex-5 FPGA, which is the strength of SR-TCAM because currently classical TCAMs cannot be implemented on FPGA. We have used two...
Dynamically reconfigurable architectures, which can offer high performance, are increasingly used in different domains. High-speed reconfiguration process can be carried out by operating at high frequency but can also augment the power consumption. Thus the effort on increasing performance by accelerating the reconfiguration should take into account power consumption constraints. In this paper, we...
An optimal algorithm for Multi-Processor Allocation in GPU system that reduce power consumption while maintain the application required performance is presented in this paper. Power consumption and heat dissipation have become critical issues in modern high performance computing systems due to the rising cost of electricity and the cooling infrastructure. The Multi-Processor Allocation (MPAlloc) algorithm...
The efficient use of embedded systems relies heavily on appropriate strategies to optimize the execution time and power consumption. These systems are characterized by resource restrictions, including the amount of memory available for applications. However, there are several techniques that make the embedded systems more efficient. One of those techniques is the code compression; the proposals found...
Biological vision systems use saliency-based visual attention mechanisms to limit higher-level vision processing on the most visually-salient subsets of an input image. Among several computational models that capture the visual-saliency in biological system, an information theoretic AIM(Attention based on Information Maximization) algorithm has been demonstrated to predict human gaze patterns better...
This paper presents experimental measurements of power consumption for core logic of a 65-nm Cyclone III FPGA and its comparison with the value predicted by the power estimation tool. The laboratory work is described, including the measurement setup, the benchmark circuits, and the CAD flows utilized to obtain power estimations. The selected circuits used as benchmarks were different type of multipliers...
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