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Run-time reconfigurable computing systems can offer increased flexibility when compared with traditional systems, a feature which can make them attractive for space-borne computing applications. This flexibility can allow a system to adapt to changes in operating conditions, such as reductions in available power, reductions in available resources (wither due to increases in task deployment, or due...
Achieving low power consumption, size reduction, and space optimization are all challenges in resource-constrained wireless devices such as Wireless Sensor Network (WSN) nodes. For instance, WSN nodes use duty cycle to improve their power efficiency, and wake-up radio (WUR) is used as a control channel to wake the nodes up. With its highly flexible features, a field-programmable gate array (FPGA)...
This paper presents a hardware implementation of morphological operations based on dynamic and partial reconfiguration (DPR) technique. This technique allows reconfiguring a part of the FPGA area with different functionalities at runtime. It is a promising solution toincrease performance in the system. Our design allows todesigner to choose the adequate morphological operation (erosion or dilation)...
This paper presents the power consumption analysis of two different routing architectures for mesh based FPGAs. The first architecture uses bidirectional Switch Box (SB) implemented using back-to-back tri-state drivers. The second one uses bidirectional SB implemented using tri-states and multiplexers. This paper highlights and experimentally demonstrates the benefit that can be reached by using multiplexers...
In this paper, we consider FPGA architecture optimization to reduce power consumption. We study two FPGA routing architectures. The first architecture uses bidirectional Switch Box (SB) implemented using back-to-back tri-state drivers. The second one uses bidirectional SB implemented using tri-states and multiplexors. Experimentation shows that when we use bidirectional SB based on tri-states and...
FPGA is considered to be a good platform for rapid prototyping of embedded designs. The power consumption is a growing problem with FPGAs, which is required to be optimized. In this paper, a method is proposed to estimate the dynamic power consumption of Micro Blaze based processing unit used in embedded designs for FPGA. The proposed method is based on experimental bench of implemented designs where...
Achieving low power consumption, size reduction, increased efficiency, and space optimization are all challenges in Wireless Sensor Networks (WSNs). WSNs use duty cycle to improve its power efficiency, and wake-up radio (WUR) is used as a control channel to wake up WSN nodes. With its highly flexible features, a field-programmable gate array (FPGA) is one of the attractive candidates for implementing...
Content Addressable Memory (CAM) is a special memory that accomplishes search operation in a single clock cycle but CAM has disadvantages like low bit density and high cost per bit. In this paper, we present an implementation of a 512 x 36 SRAM-based TCAM (SR-TCAM) on a Virtex-5 FPGA, which is the strength of SR-TCAM because currently classical TCAMs cannot be implemented on FPGA. We have used two...
Biological vision systems use saliency-based visual attention mechanisms to limit higher-level vision processing on the most visually-salient subsets of an input image. Among several computational models that capture the visual-saliency in biological system, an information theoretic AIM(Attention based on Information Maximization) algorithm has been demonstrated to predict human gaze patterns better...
Power efficient solution is essential for the portable electronic system. This paper presents an FPFA based embedded system for low power message display. Scanning technique is used to minimize the power. Experiment is conducted on 30 seven segments where an FPGA based intelligent controller scans all the display elements continuously at a certain speed to ensure only one display unit is on and other...
Security at low cost is an important factor for cryptographic hardware implementations. Unfortunately, the security of cryptographic implementations is threatened by Side Channel Analysis (SCA). SCA attempts to discover the secret key of a device by exploiting implementation characteristics and bypassing the algorithm's mathematical security. Differential Power Analysis (DPA) is a type of SCA, which...
Low power techniques in a FPGA implementation of the hash function called Luffa are presented in this paper. This hash function is under consideration for adoption as standard. Two major gate level techniques are introduced in order to reduce the power consumption, namely the pipeline technique (with some variants) and the use of embedded RAM blocks instead of general purpose logic elements. Power...
Power optimization has become one of the most challenging design objectives of modern digital systems. Although FPGAs are more and more used, they are however still considered as power inefficient compared to standard-cell or full-custom technologies. New dedicated design approaches are thus needed to reduce this gap. In this paper, we address low-power design on FPGA through a dedicated High-Level...
The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGA-based systems. The clock-gating techniques are used to reduce the total power of the system. To achieve this, we reduce clock power consumption of the system by switching-off the clock signal for the parts of system that are not used. The system presented in this paper is based on the main...
This paper describes parallel processor architecture for a mixed integer linear programming (MILP) solver to realize motion planning and hybrid system control in robot applications. It features pipeline architecture with an MILP-specific configuration and two-port SRAM. Based on the architecture, both FPGA and VLSI implementations have been done to solve sample problems including 16 variables. The...
Square root is one of the fundamental arithmetic operations in signal and image processing algorithms. This article presents a novel pipelined architecture to implement N-bits fixed point square root in FPGA using non-restoring algorithm. Pipelining hazards were avoided by modifying the non-restoring algorithm resulting in a 30% improved latency time. Furthermore, the proposed architecture is flexible...
Security devices are vulnerable to differential power analysis (DPA) that reveals the key by monitoring the power consumption of the circuits. In this paper, we present the first DPA attack against an FPGA implementation of the camellia encryption algorithm with all key sizes and evaluate the DPA resistance of the algorithm. The Camellia cryptographic algorithm involves several different key-dependent...
This paper presents hardware implementations of a DES cryptoprocessor with masking countermeasures and their evaluation against side-channel attacks (SCAs) in FPGAs. The masking protection has been mainly studied from a theoretical viewpoint without any thorough test in a noisy real world designs. In this study the masking countermeasure is tested with first-order and higher-order SCAs on a fully-fledged...
To secure cryptography hardware implementation many works are focusing on side-channels attacks. For such attacks, several different countermeasures can be done at different levels abstraction. But all published countermeasures lead to a significant area and power consumption overhead. In this paper, we present a new countermeasure against DPA attack which also leads to very small implementation compared...
The automotive industry is now facing many problems and challenges that put many restrictions on car design, towards the minimization of the car cost. Most of the problems arise from the continuously increasing need to provide more advanced features in the modern cars. This lead to a dramatically increase in the percentage electronics inside the car, which lead to increasing the number of Electronic...
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