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Achieving low power consumption, size reduction, and space optimization are all challenges in resource-constrained wireless devices such as Wireless Sensor Network (WSN) nodes. For instance, WSN nodes use duty cycle to improve their power efficiency, and wake-up radio (WUR) is used as a control channel to wake the nodes up. With its highly flexible features, a field-programmable gate array (FPGA)...
Achieving low power consumption, size reduction, increased efficiency, and space optimization are all challenges in Wireless Sensor Networks (WSNs). WSNs use duty cycle to improve its power efficiency, and wake-up radio (WUR) is used as a control channel to wake up WSN nodes. With its highly flexible features, a field-programmable gate array (FPGA) is one of the attractive candidates for implementing...
Wireless sensor networks (WSNs) are networks of battery-powered sensing devices connected with wireless interfaces. Energy consumption and processing efficiency are relevant characteristics for these systems, thus energy-efficient architectures are required. Recent works show that FPGAs are suitable candidates for efficient data signal processing in WSNs. In this work, we evaluate Flash-based FPGA...
A System-on-Chip (SoC) offers an optimal implementation of electronics for portable medical systems and in particular for Body Area Network (BAN) applications. It integrates as much functionality as possible into a single chip thereby allowing miniaturization of the system, while optimizing performance and power consumption. Using today's mature and cost effective semiconductor process CMOS technology...
Networks consisting of many autonomous sensors are gaining importance. Most wireless sensors have small batteries and must therefore be designed to consume very little power. In this paper, an approach for whole-system simulation for ultra-low power wireless sensor networks is proposed. To be able to estimate the power consumption of the whole network, the simulation framework must not only simulate...
We propose the use of a reconfigurable hardware architecture to reduce the power consumption of small sensor node that has various sensors and wireless communication facilities, that were the result of an adaptive function specialization mechanism. Traditional sensor nodes must have had a powerful and multi functional Micro-Controller Unit (MCU) to satisfy the requirements for processing any kinds...
In this paper we present preliminary results regarding data processing approach to energy efficiency of wireless and untethered field programmable gate array (FPGA)-based embedded systems. Re-configurability of FPGA allows for significant flexibility in its applications to embedded systems. However, high power consumption (caused by such flexibility) influences the designing process significantly...
Wireless sensor network (WSN) applications demand ultra low power devices. Digital Ultra Wideband (UWB) transceiver can be used as the communication module in a WSN due it its potential for location tracking, ranging and low data rate communication. Current digital UWB receiver architecture incorporates heavy parallelism, which significantly increases power consumption, especially during the acquisition...
In this paper we propose a new reconfigurable architecture for sensor nodes, called RANS-300, which can operate in applications demanding low power to high performance, although sacrificing the lifetime of the sensor node. This node has a FPGA board, which can be dynamically reconfigured to add new configuration, and has a Compact Flash device to expand the node possibilities
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