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As location sensing devices are becoming ubiquitous, overwhelming amounts of data are being produced by the Internet-of-Things-That-Move. Though analyzing this data presents significant business opportunities, new techniques are needed to attain adequate levels of processing performance. One example is the recently introduced geohash geographical coordinate system that is mainly used for indexing...
Although in recent years multi-core processors have left their academic niche and became more and more popular, the need for energy efficient and powerful devices could not been fulfilled completely. Therefore, the focus in research as well as in industry is nowadays drawn to new architecture concepts especially heterogeneous computing architectures. Unfortunately, the design and programming of these...
The paper describes the use of an FPGA Spartan-3E board in a Digital Logic Design course to synthesize music for students who have no or minimal background in Electrical and Computer Engineering. The authors hope that this paper may be used as a reference to build a better Digital Logic Design course.
Recent progress in High-Level Synthesis (HLS) techniques has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-generated RTL, involves lengthy logic synthesis and physical design flows. Moreover, mapping of different levels of coarse grained parallelism onto hardware spatial parallelism affects the final FPGA-based performance both...
This paper introduced the technical requirements and the realization method of multi-channel data acquisition circuit, proposed some solutions to eliminate channel crosstalk. The design can finish to sampling 32 channel analog signals and convert them based FPGA as a core-logic controller, this device has been successfully applied in a comprehensive telemetry device.
Intrusion Detection Systems have to match large sets of regular expressions to detect malicious traffic on multi-gigabit networks. Many algorithms and architectures have been proposed to accelerate pattern matching, but formal methods for reduction of Nondeterministic finite automata have not been used yet. We propose to use reduction of automata by similarity to match larger set of regular expressions...
Proliferation of handheld devices and growing interests in pervasive computing has led to the need for more flexible communication solutions where a single device integrates various wired and wireless communication standards e.g. Asymmetric Digital Subscriber loop (ADSL), Very high speed Digital Subscriber Loop (VDSL), Digital Audio Broadcasting (DAB), Digital Video Broadcasting (DVB-T/H) and 802...
This paper introduces and details a Built-In Self-Test (BIST) approach designed for the embedded Block Random Access Memories (BRAMs) found within Xilinx Virtex-5 Field Programmable Gate Arrays (FPGAs). The BIST is designed to test the BRAMs in all configurable modes of operation including single-port, dual-port, first-in first-out (FIFO), first-in first-out with error correcting code (FIFOECC), and...
Reduced Precision Redundancy (RPR) is demonstrated as a new method for improving fault tolerance in Field Programmable Gate Arrays (FPGAs) replacing Triple Modular Redundancy (TMR) to protect against the Single Event Effects due to radiation in arithmetic processes. As a test of this approach, the RPR technique was used to implement a Radix-4 Fast Fourier Transform (FFT). This design was implemented...
This paper presents an efficient algorithm to detect the global topological similarity between two circuits. By applying the proposed circuit similarity algorithm in an incremental design flow, IDUCS (incremental design using circuit similarity), the design and optimization effort in the previous design iterations is automatically captured and can be used to guide the next design iteration. IDUCS...
The Field Programmable Gate Array (FPGA) components offer effective solutions and provide real-time computation performances for control algorithms of electrical systems. The aim of this paper is to present the FPGA implementation of an Automatic Tracking Observer (ATO) for the synchronization of the grid voltage vector. This application is particularly useful for the control of a three-phase Pulse...
The design flow of Fast Fourier Transform devices development using the method of algorithmic operation devices synthesis from graphical representation of algorithms is proposed. Their automatic synthesis for various numbers of input data with different word length and their comparative evaluation are performed.
As the possibilities and the technology offered by the reconfigurable devices is improving constantly, reconfigurable computing is becoming a research area of interest for many researchers. Till date FPGA is the core device for reconfigurable computing. On the fly partial reconfiguration (PR) is an attractive feature of FPGA, which has opened up new directions for researchers. The feature allows multiple...
As semiconductor manufacturing continues towards reduced feature sizes, yield loss due to process variation becomes increasingly important. To address this issue on FPGA platforms, several variation aware design (VAD) methodologies have been proposed. In this work we present a practical method of process variation characterization (PVC) to facilitate VAD using only intrinsic FPGA resources. The scheme...
FPGA implementation tool turnaround time has unfortunately not kept pace with FPGA density advances. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or quality of results. As in many multithreaded applications, communication and synchronization incur significant overheads. Even if these challenges are overcome, the large graph data structures used can quickly...
The design and implementation of a sparse matrix-matrix multiplication architecture on FPGAs is presented. Performance of the design, in terms of computational latency, as well as the associated power-delay and energy-delay tradeoff are studied. Taking advantage of the sparsity of the input matrices, the proposed design allows user-tunable power-delay and energy-delay tradeoffs by employing different...
Distributing a hardware design across multiple physical devices is difficult-splitting a design across two chips requires considerable effort to partition the design and to build the communication mechanism between the chips. Designers and researchers would benefit enormously if this were easier as it would, for example, allow multiple FPGAS to be used when building prototypes. To this end we propose...
Control the data flow between device interfaces, processing blocks and memories in a vision system is complex in hardware implementation. In the research, high-level synthesis tool is used to design, implement and test the vision system within the context of required control, synchronization, and parameterization on a processor based platform. In addition, both HLS tools and HDL were used for the...
This paper is purely a design circuit to implement Partial Discharge (PD) detection in FPGA technology using Xilinx ML405 board (Virtex 4) and real time ADC in microcontroller PIC 16F877A. The research involve ISE Simulator version 10.1i (Xilinx) and ISE Xilinx Synthesized Technology (XST) using Very high integrated circuit Hardware Description Language (VHDL) programming to evaluate the use of Field...
Breadth-first Search (BFS) is a fundamental graph problem. Due to the irregular nature of memory accesses to graph data structures, parallelization of BFS on cache-based systems leads to poor performance. Many issues, such as memory access latency, cache coherence policy, and inter-process synchronization, affect the throughput performance of BFS on such systems. In our proposed message-passing multi-softcore...
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