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An excessive switching activity during the functional capture cycles of scan-based tests can lead to overtesting of delay faults. Low-power test generation procedures that address this issue consider the switching activity of the fault-free circuit. This paper observes that an excessive switching activity in a faulty circuit can also affect the test application process. In particular, we show that...
Power has becomes one of the crucial parameter while designing a SOC ICs. Power analysis of a circuit is important for reliability check, better design of power distribution network, packaging decisions and to solve power issues during test. High switching at a time demands high instantaneous current from power supply network. Which gates experience Vdd drop leading to increase in delay of the circuit...
Various formalisms deal with time, and each of them has its own notion of time. When designing a system, it is often desirable to combine several of these formalisms to model different parts. Therefore one has to reconcile execution traces that may use different kinds of time (discrete, continuous, periodic) and different time scales (e.g. minutes, microseconds or even angles in degrees). In this...
Trace buffer technology allows tracking the values of a few number of state elements inside a chip within a desired time window, which is used to analyze logic errors during post-silicon validation. Due to limitation in the bandwidth of trace buffers, only few state elements can be selected for tracing. In this work we first propose two improvements to existing “signal selection” algorithms to further...
Multistage interconnection networks (Banyan networks) are proposed as connections in multiprocessor systems and in high-bandwidth network switches. In order to achieve suitable solutions when designing such networks to fit a given task, performance evaluation plays a crucial part. This paper presents an approximative analytical modeling approach that offers a performance measure (in addition to mean...
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