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A novel Denial-of-Service attack for Networks-on-Chip, namely illegal packet request attack (IPRA), has been proposed and measures to mitigate the same have been addressed. Hardware Trojans, which cause these attacks, are conditionally triggered inside the routers at the buffer sites associated with local core, when the core is idle. These attacks contribute to the degradation of network performance...
More and more businesses are deploying their application(s) with different cloud providers which are close totheir customers in order to provide better Quality of Service(QoS) to their end customers. In this work, an optimized andsecure software-defined overlay network is proposed as an efficientmechanism to interconnect these geographically-dispersedapplications compared to using only plain IP routing...
Thanks to their flexibility and their simplicity of installation, Wireless Mesh Networks (WMNs) allow a low cost deployment of network infrastructure. They can be used to extend wired networks coverage allowing connectivity anytime and anywhere. However, WMNs may suffer from drastic performance degradation (e.g., increased packet loss ratio and delay) because of interferences and congestion. Generally,...
In the common implementation of software defined networking where only one controller is used, tasks required by various applications may overwhelm the controller as the network grows, leading to degradation of the network performance. Some multi-controller architectures have been proposed to remedy such scalability issue. In this paper, we present our design and implementation of a routing application...
Mesh-Tree architecture is an enhanced architecture in NoC. In a three dimensional Mesh-tree topology every layer may be treated as mesh and trees are used to connect adjacent layers. This type of architecture is very efficient for broadcasting as well as high speed communication. Chip multiprocessors are becoming more widely utilized to efficiently use the increasing number of transistors available...
In this paper, we propose a Network on Chip router architecture with increased reliability, energy efficiency and with reduced area overhead. The proposed router architecture model adjusts dynamically to the error control strengths of the layers of NoC. In this paper, we target to optimize the combined operations of arbiter and multiplexer by using a Merged Arbiter Multiplexer (MARX) along with a...
In this paper we present a concept of a reconfigurable logic toolchain. The specialty of this toolchain is the highly configurable architecture design. The goal is to provide the designer with the ability to suit the architecture of the reconfigurable logic to a specific application domain, for example communication or image processing. Thereby the disadvantages of very flexible, universal structures...
Wireless mesh networks (WMNs) are the key technology of wireless access network for wireless Internet application. WMNs exploit mesh gateways for delivering traffic to or from the end-users with a multihop wireless backbone. Because the traffic volume is expected too high for single mesh gateway, the adoption of multiple mesh gateways is very essential. Hence, a traffic balancing algorithm becomes...
Quantum walks can be implemented in the hypercube and general graphs, where hypercube is a regular graph. According to quantum walk algorithm, unitary property of quantum walks can be preserved. In the regular graph, to develop quantum walks algorithm is focused on quantum search algorithm. Quantum switching is the reversible and parallel computation circuits, where parallel computation circuit can...
Transformation of PSTN to NGN is a challenging goal for many legacy telecom operators. A smooth migration for PSTN will be an evolutionary process. It is expected that a new generation PSTN can extend the range of new services. Chunghwa Telecom is currently initiating an NGN_CN development which is part of NGN project for PSTN migration. In this paper, the key network technologies for PSTN migration...
Most NML research has studied small magnet ensembles for interconnect or isolated gates. We discuss how NML might be used to process information, as well as suitable system architecture-to-device architecture mappings. A case study for pattern matching hardware is presented.
A Hierarchical Torus Network (HTN) is a 2D-torus network of multiple basic modules, in which the basic modules are 3D-torus networks that are hierarchically interconnected for higher-level networks. Three deadlock-free adaptive routing algorithms called link-selection, channel-selection, and a combination of link-selection and channel-selection was proposed for the efficient use of physical links...
Network-on-Chip (NoC) architecture is considered to be an attractive solution to overcome the combined problems of limited bandwidth and scalability in multicores. Input buffering at the router allows the network to sustain the accepted throughput without performance degradation. However, the input buffers consume a substantial portion of the total power budget, and there have been proposals to reduce...
Multi-threshold CMOS (MTCMOS) is currently the most popular methodology in industry for implementing a power gating design, which can effectively reduce the leakage power by turning off inactive circuit domains. However, large peak current may be consumed in a power-gated domain during its sleep-to-active mode transition. As a result, major IC foundries recommend turning on power switches one by one...
We propose the use of a mutually complementary communication protocol (MCCP) based on destination oriented directed acyclic graph (DODAG) using multi-interface communications. Recently, research on smart home is getting more active because of the public opinion on energy saving or comfortable living. The architecture of smart home includes sensor networks that are important infrastructure to collect...
Placement is considered a fundamental physical design problem in electronic design automation. It has been around so long that it is commonly viewed as a solved problem. However, placement is not just another design automation problem; placement quality is at the heart of design quality in terms of timing closure, routability, area, power and most importantly, time-to-market. Small improvements in...
In this paper, a new countermeasure against power and electromagnetic (EM) Side Channel Attacks (SCA) on FPGA implemented cryptographic algorithms is proposed. This structure mainly focuses on a critical vulnerability, Early Evaluation, also known as Early Propagation Effect (EPE), which exists in most conventional SCA-hardened DPL (Dual-rail with Precharge Logic) solutions. The main merit of this...
In this paper, a low-power flip-flop standard cell with gate-length biasing technology is introduced into SMIC 130nm CMOS libraries for low-leakage applications. The flip-flop standard cell based on the transmission gate with master-slave structure is optimized to achieve low energy delay product (EDP) by using gate-length biasing. The layout, abstract design and standard-cell characters of the low-power...
In the wireless communication networks, quantum message integrity can be applied with quantum authentication and quantum signature if the source and destination are indirect communication. Eavesdroppers and malicious nodes may exist in the routing path from the source to the destination. There is major threat in the indirect communication. Based on quantum nature, we design quantum permutation model...
Looking for usable gateway is a process, which brings the biggest overhead, in MANET accessing Internet. For controlling the routing overhead effectively, a gateway discovery method for MANET accessing Internet based on overhead control, which is according to the similar between ant searching path and mobile node searching gateway, is proposed in this paper. By simulating the pheromone's update process...
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