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A Range Pre-selection Sampling (RPS) technique is introduced to reduce the input drive energy for SAR ADCs and is applied to a 10-bit 2MS/s SAR ADC in 65nm CMOS in this paper. Using the proposed RPS technique, the peak input sampling current and hence the input drive power requirement is reduced by a factor 2.4 as compared to conventional sampling (CS). Considering an ideal Class A operation for the...
This paper proposes the reconfigurable RX analog baseband transformer that supports multi-standard applications. The proposed ABB can transform its structure between a delta-sigma modulated ADC for narrow band and a baseband LPF for wide band with a simple switch configuration without extra cost. Thus, the ABB obtains efficiency in both size and power aspects. It occupies only 0.11mm2 of active area...
A novel concept instrumentation amplifier (IA) using an analog signal compression technique is suggested to achieve a large dynamic input range. A large analog input signal is segmented into a smaller analog signal to prevent saturating the analog output signal in the input stage of the IA. At the input stage, we apply a reference bias at a node between an input capacitor and an input MOS to function...
This paper presents a low power, area efficient 11bit single-ended successive-approximation-register (SAR) analog-to-digital converter (ADC) with small loading effect targeted for biomedical applications. The design features an energy-efficient switching technique with an error cancelling capacitor network to cover an input range twice the reference voltage. The ADC's loading effect to previous stage...
Low-power designs are a necessity with the increasing demand of portable devices which are battery operated. In many of such devices the operational speed is not as important as battery life. Logic-in-memory structures using nano-devices and adiabatic designs are two methods to reduce the static and dynamic power consumption respectively. Magnetic tunnel junction (MTJ) is an emerging technology which...
In this paper, a novel 10 bit 20 MS/s, low power, pipelined ADC using both capacitor and opamp sharing techniques is proposed. In the proposed ADC, feedback capacitors in the first four stages are shared between adjacent stages in order to decrease the power dissipation of the opamps used in these stages. The opamps in the six pipeline stages are also shared between adjacent stages in pairs for further...
This paper introduces an architecture and design for high resolution, high linearity Nyquist rate SAR ADCs requiring only a single simple calibration at startup. The proposed architecture benefits from an intrinsically linear 1.5 bit ΣΔ DAC to resolve the fine bits of the SAR ADC after a coarse conversion phase with a monotonically switched capacitive DAC. The ΣΔ DAC is also used for a single shot...
A novel pixel architecture for CMOS image sensors is presented. It uses only one amplifier for both integration of the photocurrent and in-pixel noise cancelation, thus minimizing power consumption. The circuit is specifically designed to be used in readout systems for lateral flow immunoassays. In addition a switching technique is introduced enabling the use of column correlated double sampling technique...
This paper proposes a self-interference-resilient LNA for the FDD-LTE covering 0.7 to 1GHz. It incorporates a switched-LC N-path network with gain-boosting and optimum-biasing techniques to enhance the out-of-band (OOB) linearity at ≥40MHz offset. Implemented in 0.18µm SOI CMOS, the LNA achieves >31.2dB output rejection, +26.2dBm (+8dBm) OOB-IIP3 (iB1dB) at ≥40MHz offset and 6.8dB blocker NF at...
This paper presents a 0.9V-VDD sub-nW CMOS voltage reference based on dynamic operation with the absence of large resistors, hence occupying small chip area. The proposed voltage reference is based on the threshold voltage difference between high-Vt and normal-Vt transistors. Switched capacitors are used instead of resistors to reduce chip area and to enable dynamic operation. Moreover, the dynamic...
This paper presents a new circuit technique named as “residue oversampling,” which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying dynamic element matching (DEM), the impacts of capacitor mismatch and noise upon the successive-approximation register (SAR) ADCs are diminished significantly without calibrations. The proof-of-concept prototype...
This paper presents a 13-bit fully-differential successive approximation register analog-to-digital converter with a hybrid DAC that is suitable for sensor applications. An innovative dithering plus averaging technique is developed around this originally-designed 10-bit ADC to make it possible to attain an effective resolution of 13 bits in a configurable fashion without calibration. The ADC has a...
The proposed 1.8-V 10-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC) for electrocardiographic (ECG) monitoring applications has two operation modes suitable for the dichotomous activity of ECG signals: full and reduced switching modes. MSBs tracking and LSBs extrapolation run in full and reduced switching mode, respectively, for smooth mode changes adaptive to...
Energy harvesting systems are becoming an exciting alternative for powering low-power electronics. For applications where real time response is not mandatory, energy harvesting systems can also be used with electronic devices whose power demand exceeds available power. Hence, it operates in two phases: charging and discharging phase. For switching between these two operating phases a power management...
This paper reports 2.37–5.94 GHz multicore CMOS LC Digitally-Controlled Oscillator (DCO) designed in 65 nm RF CMOS technology. The three cores of 6-bit switch capacitor array provides wide LC-DCO tuning range. With 1.8 V supply voltage, simulation results show that the tuning range is from 2.37 GHz to 5.94 GHz, while average phase noise value across the entire tuning range is −135 dBc/Hz. Power dissipation...
Aiming at the application of neural signal detection system, this paper designs a 12-bit 200KS/s high resolution successive approximation analog-to-digital converter (SAR ADC) fabricated in SMIC 0.18-μm process. An optimized digital self-calibration technique is proposed to correct the static offset of the comparator and the mismatch of the capacitor array by using a correction capacitor array, achieving...
A 10bit 40MS/s asynchronous timing logic successive approximation analog-to-digital converter (SAR ADC) is presented, including a bootstrapped switch, a charge redistribution digital-to-analog converter(DAC) and a dynamic comparator. A redundancy compensation and a mismatch calibration are introduced to achieve conversion accuracy improvement. A monotonic capacitor switching technique is adopted to...
This paper introduces a highly energy-efficient 12-bit 280KS/s successive approximation register (SAR) analog-to-digital converter (ADC). A novel switching scheme integrated segmentation capacitor and partial-monotonic capacitor technique which can reduce the power consumption and the area is proposed. Compared with the conventional scheme, the average switching energy can be reduced by about 98%...
This paper optimizes the design of an OTA for a Switched Capacitor (SC) Integrator in a discrete time Sigma-Delta Modulator based on the total settling time requirement and by application of the gm /Id method. One of the main constraints when implementing SC Sigma-Delta ADCs for high sampling rates is the requirement for the transition frequency and settling behavior of the operational transconductance...
A switched capacitor low-pass filter employing folded-cascode CMOS OP Amps with a dynamic switching bias circuit capable of processing video signals, which enables low power consumption, and operation in wide band-widths and low power supply voltages, is proposed. In this filter, charge transfer operations through two-phase clock pulses during the on-state period of the OP Amps and a non-charge transfer...
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