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This paper presents a low-power speed-scalable 8bit Successive Approximation Register (SAR) ADC implemented in 0.18-μm CMOS. By designing a compact asynchronous controller and a charge-sharing DAC, the power consumption can be linearly scaled with the conversion speed. A maximum power dissipation of 28.4 μW and 0.019 mm2 total area make this ADC ideal for highly integrated wireless sensor nodes. The...
This paper presents a 10-bit SAR ADC using a variable window function to reduce the unnecessary switching in DAC network. At 10-MS/s and 1-V supply, the ADC consumes only 98 μW and achieves an SNDR of 60.97 dB, resulting in an FOM of 11 fJ/Conversion-step. The prototype is fabricated in a 0.18μm CMOS technology.
A single-loop third-order switched-capacitor sigma-delta modulator for hearing aid application is presented. Double-sampling is introduced to achieve a high performance with comparative low power consumption. The effect of capacitor mismatch is further discussed. To over come the switch-on problem under low-voltage, bootstrapping is adopted in this design. The modulator is implemented under SMIC 0...
This paper presents a 12-bit low-voltage low-power analog-to-digital converter (ADC). The design employs switched capacitor (SC) techniques and implements a successive approximation (SA) algorithm. The ADC is highly reconfigurable, with digitally selectable resolution and input signal amplitude, and achieves 11.4-bit of effective resolution at 500 kHz clock frequency, with a power consumption below...
In this paper, a design methodology for low-power design of very-low-voltage high-resolution switched-opamp ADCs (analog-to-digital converters) is presented. This methodology determines the optimum values of all stage capacitors, the compensation capacitors of the opamps and also the resolutions of the stages to minimize power consumption for an expected signal-to-noise ratio. The design procedure...
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