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A 28nm CMOS 1.2GHz full-duplex analog front end (AFE) is presented. The AFE can deliver 20Gbps of aggregate service across 50m of RG6 coax. The on-chip line driver, powered from a 7.2V supply and using core transistors, delivers 5.9Vptp differential to the line through the hybrid. A tunable capacitive hybrid circuit for full duplex operation is proposed for low noise performance and allows channel...
A new capacitor package and PCB embedding technique is introduced to significantly reduce the system power distribution network impedance at the pads of surface mounted integrated circuits. The capacitor is multi-layer ceramic capacitor (MLCC) that is a right cylindrical shape with via channels in the outer wall along the axis of the part. The capacitor called a Z-Directed component (ZDC) is then...
Flying capacitor multilevel (FCML) converters are known to naturally balance the capacitor voltages through the use of phase-shifted pulse-width modulation. However, in practice, the capacitor voltages can still deviate and active balancing is often required. This work investigates the origins of the voltage imbalance in practical implementations of such converters and presents corresponding solutions...
paper proposes application of a DC/DC Z-Source Converter (ZSC) based on the one-port impedance network, operating in continuous conduction mode (CCM) for solar power generation in DC microgrid. A photovolaic array is connected to the input of ZSC, which provides voltage gain from 167V. The nominal input power of arrangement was 1440 Watts. Attending the low efficiency of photovoltaic modules (PV)...
The front-end amplifier forms the critical element for signal detection and pre-processing within neural monitoring systems. It determines not only the fidelity of the biosignal, but also impacts power consumption and detector size. In this paper, a combined feedback loop-controlled approach is proposed to neutralize for the input leakage currents generated by low noise amplifiers when in integrated...
In this paper, we investigate the impact of the PDN inductance/impedance as well as the decoupling capacitors location on the initial IC noise voltage drop for a high performance system. To consider a worst case situation for the noise voltage at the integrated circuit (IC) we set the on-chip capacitance to zero. The impact of the delay due to remote location of the decoupling capacitors for fast...
This paper presents the design of a power amplifier integrated in a CMOS 180 nm technology, which is intended to drive an inductive link operating at 990 MHz. A class-D topology is employed to avoid the use of inductors. A design methodology is proposed to find the optimal transistor width, solving the trade-off between the ON-resistance and gate capacitance. The area occupied is 1.5 mm2, most of...
This paper presents a method of implementing a large virtual capacitor using an area-efficient capacitance multiplier circuit. The multiplier solves the major issue of large area consumption in integrated circuits needing high capacitance values. The proposed architecture improves other important parameters, such as the quality factor and the operating signal range. An analytical equivalent model...
A novel design of voltage-mode (VM) all-pass filter (APF) utilizing a single dual-X current conveyor (DXCCII) is proposed. Although many other voltage mode first-order APFs are available in literature, however majority of them cannot allow us to get high input impedance, low output impedance and grounded capacitor properties together. The proposed circuit offers these properties with reduced number...
Electromagnetic rail launcher has a wide range of applications. Inductive shunt device is usually paralleled with the rails of the launcher as an approach to limit muzzle arc by transferring armature current. The shunt parameters will significantly influence the rail current, armature velocity and device stress conditions, which also makes the physical process more complicated. In this paper a circuit-electromagnetic-mechanical...
In the field of CMOS Integrated Circuits (IC), there are several types of Analog to Digital Converters (ADC). Every architecture rules its own region of operating conditions. The high level parameters which categorize ADC's are Speed and Resolution. Pipelined ADC rules the region where the Speed and Resolution are moderate. More specifically, Resolution varies from 8 to 16 Bits, Speed varies from...
This paper presents a biopotential analog front-end (AFE) IC for measuring electroencephalogram (EEG). The AFE is based on the AC-coupled chopper stabilized instrumentation amplifier architecture to achieve the low noise. To increase the input impedance, the capacitive input impedance boosting loop (CIIBL) is proposed. The CIIBL forms a positive feedback loop between input and output of the instrumentation...
Signal return path discontinuities, parasitic inductance and impedance mismatch within interconnects are major factors that contribute to degraded high-speed signal quality in three-dimensional (3D) integrated circuits and systems. In this paper, we apply an alternate power delivery method and a novel I/O signaling scheme to a 3D system to address these issues. Two test vehicles made of stacked PCBs...
An architecture of a programmable gain integrating amplifier is presented. The circuit operates using two clock phases for sampling and amplification and the gain is defined by the ratio between the pulse-width of a control signal and the integrator time constant, which is defined by a resistor and capacitor. The proposed architecture also has configuration switches that enable its use in the modes...
In a power distribution network (PDN) design, it is desirable to have a clean, undistorted power supply from the voltage source to each of the individual transistors in order for an integrated circuit (IC) to function properly. The optimum design for such PDN is to provide a large individual power plane from the power supply to each of the interfaces in the IC. However, due to form factor limitation...
This paper presents a new versatile multifunction voltage-mode biquadratic filter with three inputs and four outputs employing single-ended operational transconductance amplifiers (OTAs) and grounded capacitors. The proposed circuit provides the following advantages: (i) employment single-ended OTA and grounded capacitor which is highly suitable for integrated circuit implementation, (ii) simultaneously...
The simulation and the analysis of a power distribution network (PDN), termed power integrity (PI), are performed in the frequency domain and primarily involve analyzing the power and ground planes and the decoupling capacitors. The capacitors provide a temporary source of localized energy for instantaneous current demands from a IC, and a low-impedance return path for high frequency noise. Capacitors...
Optimizing decoupling capacitor placement to insure rapid charge delivery is discussed in this paper. Placing additional decoupling capacitors in close proximity may reduce effective inductance but this inductance is only reduced under certain conditions.
The conducted RF immunity of microcontrollers is sometimes strongly frequency dependent. This paper discovers one origin of the frequency behavior of the immunity of microcontrollers against electromagnetic disturbances on oscillator pins. The behavior is explained by considering resonances in current loops through oscillator pins. The proposed theory is verified by systematically measurements.
The design of power distribution networks (PDNs) on printed circuit board (PCB) structures, or even on interconnect structures inside IC packages, typically results, with or without decoupling capacitors added, in a network full of impedance resonances. These resonances functionally hamper fast digital and RF designs from several MHz up to the GHz-range onwards and are the root cause for many EMC...
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