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A wireless transmitter using RF pulse-width-modulation (PWM) with carrier switching is introduced. The proposed approach overcomes the dynamic range limitation of PWM at radio frequencies by utilizing carrier switching between fundamental and half-fundamental frequencies, depending on the signal level to be transmitted. This allows for transmission of signals with large peak-to-average power ratio...
An analog current-based 1:16-demultiplexer with integrated sample-and-hold is presented. It is designed in a 28 nm CMOS technology and is the basis for a 16-fold time-interleaved ADC. It offers sampling rates up to 64 GS/s, while consuming only 0.9 W of power and 2.6 mm2 of chip area.
The frequency doubler(FD) circuit has found immense use in digital CMOS systems. Such a circuit is especially useful in a clock distribution network where the clock signal can be distributed at a low frequency and multiplied (clock frequency made 2 or 4 times) at the blocks where a higher frequency is needed. This reduces the power consumption of the clock distribution network. Clock Frequency Multiplier...
An all-digital de-skew clock generator for arbitrary wide range delay is proposed to minimize the instability of the clock settling while achieving fast locking time. The clock skew problem is detrimental in high-speed applications, especially when the skew is longer than multi-cycles. The proposed clock generator was fabricated in a 0.18-μm CMOS technology. The clock generator achieves a measured...
The cores of a System-on-Chip (SoC) connected by Networks-on-Chip (NoCs) need interfaces to properly send and receive packets. However, in this interfacing, different situations can occur when heterogeneous cores are applied. Applications may require, for example, an irregular traffic behavior or present a large bandwidth variation. These situations may lead to problems in data synchronization. In...
Based on the principle of Pipeline ADC, a 10-bit, 50-MS/s pipeline A/D converter is presented in this paper. Combining with bootstrap circuit and bottom-plate sampling technology, a high linearity on-chip sample-and-hold (S/H) is realized. This ADC is optimized for high static and dynamic performance applications in imaging and digital communications. It operates at 1.2 V power supply and achieves...
This paper proposes a packet-based verification platform with serial link interface for emulating the hardware of the heterogeneous IPs before tape out. With the serial link interface Serializer/Deserializer (SerDes) added between IPs, significant amount of pin counts can be reduced in the platform. An adapter is inserted between IP and SerDes to convert parallel bus into packets and handle the handshaking...
A 118.4 GB/s multi-casting network-on-chip (MC-NoC) is developed as communication platform for a real-time object recognition processor. To support application-specific data transactions, the MC-NoC adopts the combination of hierarchical star and ring topology with the multi-casting capability. As a result, the proposed MC-NoC improves data transaction time and energy consumption by 20% and 23%, respectively,...
This paper describes a 6 bit 1 GS/s CMOS flash A/D converter using dual-bootstrapped THA circuit. The proposed flash architecture employs bootstrap technique in the track and hold circuit for low bit error ratio and high linearity. The measurement result shows a conversion rate of 1Gs/s, SNDR of 35.1dB, DNL/INL of plusmn0.65LSB/plusmn0.80LSB, and power dissipation of 228 mW at 1.8 V. The chip is implemented...
The high performance switch plays a critical role in the high performance computer (HPC) system. The applications of HPC not only demand on the low latency and high bandwidth of the switch, but also need the effective support of collective communication, such as broadcast, multicast, and barrier etc. In this paper, HPP switch, as the core component of interconnection network of a HPC prototype, is...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
MOS analog switch resistance of devices with low supply voltage is drastically reduced by synchronous voltage multiplication of the clock signals. Application to a SC bandpassfilter makes a higher sampling rate (260 kHz) feasable with low supply voltage (?? 1.5 V) and low power consumption (240 ??W).
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