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The interest to use Switched Ethernet technologies in real-time communication is increasing due to its absence of collisions when transmitting messages. Nevertheless, using COTS switches affect the timeliness guarantee inherent in potentially overflowing internal FIFO queues. In this paper we focus on a solution, called the FTT-SE protocol, which is developed based on a master-slave technique. Recently,...
Ethernet switches are increasingly used in real-time distributed systems as a technical solution to guarantee the timeliness in communications. However, there are still limitations related to real-time behavior caused by the limited number of priority levels and the possibility of memory overruns with consequent message losses. These limitations can be eliminated using a master/slave technique such...
Ethernet is an evolving standard, not a static one. It's a family of frame-based networking technologies and communication services offering different communication capabilities and quality of service to distributed applications. Ethernet is becoming more present in critical embedded systems because of the supporting software and hardware ecosystem, and guaranteed growth path supported by different...
Targeting the distribution of accurate frequency and time references across Packet Switched Networks (PSNs), the IEEE Std 1588™-2008 (a.k.a. 1588V2 or PTPV2) standard specifies network infrastructure components intended to reduce the impact of network elements located between the Grandmaster clock and Slave clocks. Also referred to as On-Path Supports (OPS), these PTPV2 build-in network components...
This paper analyzes the performance of Ethernet layer congestion control mechanism Quantized Congestion Notification (QCN) during data access from clustered servers in data centers. We analyze the reasons why QCN does not perform adequately in these situations and propose several modifications to the protocol to improve its performance in these scenarios. We trace the causes of QCN performance degradation...
State of the art VLSI systems are characterised by their small, deca-nano feature size. In order to accommodate the complexity and scalability, a new design paradigm, system on chip (SoC) has been introduced. Performance and power of giga-scale SoC is ever more communication-dominated. However typical SoC communication infrastructure is based in standard buses and protocols which are difficult to...
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-to-chip interconnect which is particularly used in AMDs novel Opteron processor series. As it is an open protocol, a broad application range exists ranging from southbridge chips over closely coupled accelerators to add in cards. Its...
TTEthernet is a novel communication infrastructures that allows using a single physical communication infrastructure for distributed applications with mixed-criticality requirements, e.g. the command and control systems and audio/video systems. This is achieved via a fault-tolerant self-stabilizing synchronization strategy, which establishes temporal partitioning and, hence, ensures isolation of the...
Three applications in wireless networks where model-free stochastic learning is applicable, are discussed. The learning based optimization problems are formulated and simulation results are presented. Some open issues are also discussed.
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