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The demands of high-speed and power-efficient systems have resulted into the emergence of the approximate computing. Existing approximate circuits as well as stochastic techniques have shown promising advances in improving various figures of merit. However, a through fair comparison of arithmetic units still remains an issue which has not been studied. This paper reviews the prerequisites for a fair...
Signed binary multiplication is the essential part of all digital processing needs. The digital processing is inseparable part in microprocessor, microcontroller, digital image processing, data manipulation, etc. In this paper, a method to generate the partial products which are generated in the multiplication process is being proposed, in order to reduce the computational efforts in the multiplication...
A radix-4 energy efficient carry-free truncated multiplier is proposed and designed based on a linear array left-to-right carry-free (LRCF) multiplier [1]-[3]. In our proposed multiplier, the final product is obtained in parallel with the reduction of partial products in carry-save form using an improved on-the-fly conversion of O(n) size based on conditional adders. In addition to the proposed multiplier,...
After Fifty years of it's existence the K-means clustering is still popular among researchers due to lower computational complexity. Real time embedded applications require hardwiring of unsupervised learning algorithms like K-means within System-on-Chip for prompt processing in applications like image segmentation, pattern classification, speech recognition etc. This requirement is a must while analyzing...
Addition is the most widely utilized arithmetic operations in any adder circuits. The performance of an adder is a speed determining factor for arithmetic operations. This project is proposed to analyse and compare the performance of various adder circuits in order to obtain the design of a high throughput aging-aware variable latency multiplier. The moderate performance degradation is achieved in...
High speed multiplier designs have been the primacy for multiplier dominated applications such as wireless communications, computer applications, and image processing. In this paper a high performance fixed word length multiplier design by using recently proposed technique to eliminate the error correcting word and a delay efficient parallel prefix Ling adder for final redundant binary to normal binary...
Due to its high modularity and carry-free addition, a redundant binary (RB) representation can be used when designing high performance multipliers. The conventional RB multiplier requires an additional RB partial product (RBPP) row, because an error-correcting word (ECW) is generated by both the radix-4 Modified Booth encoding (MBE) and the RB encoding. This incurs in an additional RBPP accumulation...
Modulo adder is the key component in the residue number system. In this paper a novel modulo 2n − 2k − 1 adder is designed and implemented to generate random numbers for use in cryptographic applications. The modulus used in this paper is of the form 2n − 2k − 1 (1≤ k ≤ n-2), which is best suitable for multichannel RNS processing. The modulo 2n − 2k − 1 adder is divided into four modules the pre processing,...
Blum-Blum-Shub (x2 mod N) is proved cryptographically secure pseudorandom generator which passes all the statistical properties of randomness tests. It is secure, because it cannot predict in forward direction as well as in backward direction. The reason is hard to factorize the large integer N (≥ 264) which is the product of two special primes. The major challenge of BBS is the efficient...
A generator modulo 3 (mod 3) is a circuit that generates a residue mod 3 from a binary vector. It is an essential circuit used to construct the encoding and checking circuitry for arithmetic error detecting codes, such as residue codes mod 3 and the 3N code, as well as some residue number system hardware. In this paper, we compare speed and area of varius VLSI implementations of 16-input generators...
The main objective of this paper is to implement a multiplier for high speed and low energy applications. Multipliers are the building blocks of high performance systems like FIR filters, Digital signal processors, etc in which speed is the dominating factor. There are many multiplier architectures developed to increase the speed of algebra. Booth algorithm is the most effective algorithm used for...
In recent years of development in wireless communication many baseband processors been proposed in various fields in order to propel the demand of high performance, less effective area, this changes according to the need of future developments. This paper presents an efficient processor architecture framework with respect to power consumption and area. The proposed framework can accommodate basic...
The Booth multiplier is a very fast multiplier with minimum latencies. In this paper, a typical architecture of Booth Encoder and Wallace tree is presented, In which we have implemented pipelining at the intermediate nodes of the modules present in it. The architecture comprises of four modules, they are as follows, One's Complement generator, Booth Encoder, Partial product generator and Wallace tree...
Arithmetic circuits are some of the most common circuits, yet building generators for these circuits is usually both ad-hoc and error-prone. Often, generator designers do not directly use Register Transfer Languages, but instead use scripting languages (e.g., Perl) to generate RTL and overcome the limited expressivity of typical RTL languages. We present a new approach to generator construction, where...
In this work new efficient modulo 2^n+1 residue generators are proposed. The input operands are divided into n-bit vectors which are added by an inverted end around carry save adder tree and a final stage diminished-1 modulo 2^n+1 adder. The conversion of the proposed residue generators to configurable modulo 2^n±1 ones is also discussed. Modulo 2^n±1 residue generators find applicability as forward...
Flying-Adder frequency synthesis architecture is a comparatively new technique of generating fractional frequency derived from reference frequency. The first advantage is that system consists of pure digital circuits. The second advantage is fast response. On the other hand, this synthesizer generates a desired average frequency, which is not spectrally pure. Since its invention, it has been utilized...
Decimal arithmetic has received considerable attention recently due to its suitability for many financial and commercial applications. In particular, numerous algorithms have been recently proposed for decimal multiplication. A major approach to decimal multiplication shaped by these proposals is based on performing the decimal digit-by-digit multiplication in binary, converting the binary partial...
In this paper, we have proposed area-efficient 3-input decimal adders using simplified carry and sum vectors. By using proposed generator circuits and the recursive generation of correction terms, our proposed decimal adders could perform efficient summations with three inputs of operands. Synthesis shows that our proposed adders save up to 39.2 % area cost compared to previous reported decimal adders...
The generation of the remainder of the integer division by one or more moduli is essential in various applications involving residue number system (RNS), arithmetic error control coding, and cryptography. In this paper, we consider the possibility of designing multi-residue generators capable of sharing hardware which, unlike previous designs, are not limited to the pairs of conjugate moduli 2a −...
In this paper we present an overview of design implementation of a Symmetrical Multiple Valued Logic (SMVL) arithmetic circuit based on the use of restricted moduli Symmetrical Signed Residue Number System (SSRNS). Restricted radix-7 Symmetrical quaternary Signed digit (Rr7SqSd) T-gate based interconnections and full adders are used to implement sign detection, overflow detection and magnitude comparison...
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