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The complexity of high performance digital systems has rapidly increased. When we design such systems in a system-on-chip (SoC), lots of predesigned intellectual properties (IPs) are integrated to build a system. To verify the functionality of such systems, conventional simulation methods take extremely long time and they have limited debugging capability due to the existence of many predesigned IPs...
The off-chip memory bandwidth is often a critical part of a video processing system. Traditional cache usually behaves poor since some video algorithms, such as motion compensation, tend to access memory in an inefficient way. An efficient memory bandwidth architecture for video decoder is proposed in this paper. Two bandwidth optimization strategies are proposed through pixels reconstructed and data...
This paper propose an efficient interconnect interface, which has been applied in reconfigurable multimedia system (REMUS). In order to achieve high performance of data share between multi cores, this interconnect interface applies overlapping operation mechanism in memory. Test of H.264 HiP (High Profile) decoding shows that the data exchange rate achieves a speedup of 285% compared with the AHB...
3DTV promises to become the mainstream of next-generation TV systems. High resolution 3DTV provides users with a vivid watching experience. Moreover, free-viewpoint view synthesis (FVVS) extends the common two-view stereo 3D vision into virtual reality by generating unlimited views from any desired view point. In the next-generation 3DTV systems, the set-top box (STB) SoC requires both a high-definition...
Multimedia decoders mapped onto MPSoC platforms exhibit degraded video quality when the critical system resources such as buffer and processor frequency are constrained. Hence, it is essential for system designers to find the appropriate mix of resources, living within the constraints, for a desired output video quality. A naive approach to do this would be to run expensive system simulations of the...
Two of the most popular video coding standards, MEPG-2 and H.264, are realized on PAC Duo platform, a heterogeneous multi-core SoC containing one ARM core and two PACDSP's (Parallel Architecture Core DSP). In addition to the optimization of the video software codes, in order to fit to the architecture of PACDSP, the inter-core synchronization required by the dual core implementation must be added...
Dual-core platforms are growing as a new industry trend as platforms with only one core cannot easily perform the diverse functions in current embedded system applications, such as smart phones. We establish an easy-to-use co-simulation dual-core virtual platform to validate the functionality of hardware and software jointly. In our platform, the hardware components are implemented by SystemC, and...
Transcoding is commonly used in media servers to adapt video bitstreams to capabilities and specifications of the receiving playback devices or the transmission network channel in between. Primary adjustments are done on the video format, the resolution and the bitrate. In this paper we propose utilizing transcoding as a means of converting a regular standard video bitstream to a standard video bitstream...
Multiprocessor-system-on-a-chip will be the dominating architecture in embedded systems as it provides an increase in concurrency improving the performance of the system rather than increasing the clock speed which affects the power consumption of the system. However, concurrency needs to be exploited in order to improve the system performance in the different applications'environments. The new emerging...
In this paper motion compensation IP core design based on SOPC technology is researched, which achieves the software hardware co-design method in video decoding to overcome the drawbacks of the software decoding and hardware decoding. The design of hardware modularization which is based on the motion compensation algorithm in MPEG-4 video decoding standard is completed by using verilog HDL language...
In this paper, we propose a real-time platform for the H.264 CODEC with a memory management method, in which we use a preloading mechanism in order to reduce access to external memory. The platform uses an external DDR2 memory (to record the sequence images) and an intelligent memory controller to read the external memory periodically to load another local memory by the macroblocks (of different sizes)...
Wireless video interphone cannot only provide portability, but also connect people through video communication, so it gains more and more interest in consumer electronics. To design such systems, it needs high performance video processing engine. In this paper, a Multi-processor system on a chip (MPSoC) is designed, in which there are one 32-bit RISC CPU and a low power, high performance H.264 codec...
Power consumption becomes a very important criterion for the portable embedded devices and, therefore, many Dynamic Voltage/Frequency Scaling (DVFS) techniques have been introduced. This paper is trying to break down and analyze the power consumed by three main components, DSP logic, local memory, and the external DDR2, of a multi-core SoC platform. There are four configurations for this SoC platform:...
Design at the Electronic System-Level (ESL) tackles the increasing complexity of embedded systems by raising the level of abstraction in system specification and modeling. Aiming at an automated top-down synthesis flow, effective ESL design frameworks are needed in transforming and refining the highlevel design models until a satisfactory multi-processor system-on-chip (MPSoC) implementation is reached...
Computing-intensive algorithms which occupy most of executing time are always the main bottleneck in real-time or high quality video applications. In this paper, the optimization methods of the computing-intensive decoding algorithms of H.264, including MC (Motion Compensation), Deblocking and IDCT-IQ (Inverse Discrete Cosine Transform-Inverse Quantization), are proposed firstly, and then implemented...
The elaboration of new and innovative systems such as MPSoC (Multiprocessor System on Chip) which are made up of multiple processors, memories and IPs lies on the designers to achieve a complex codesign work. Specific tools and methods are needed to cope with the increasing complexity of both algorithms and platforms. Our approach to design such systems is based on the usage of a high level of abstraction...
This paper proposes a reconfigurable multi-processor SoC for media applications called REMUS (REconfigurable Multi-media System), which consists of 512 processing engines and two ARMs. The processing engines are divided into two dynamic configuration groups, which can be easily tailored and extended. The processing engines, DBIs (Data Buffering Interface, DBI) and context interfaces build up a large...
A System-on-Chip Design of VLD (Variable Length Decoder) in multi-standard video decoder is proposed in this paper. Our design supports all the popular video compression standards, e.g. MPEG-1, MPEG-2, MPEG-4, H.264, AVS, RealVideo. Benefit from its low power, the design is especially suitable for wearable multimedia applications. Simulation results show that the whole design takes an area of 1.04mm2,...
A flexible and high performance SoC is developed for networked media applications by integrating two RISC cores, Ethernet interface and coarse-grained configurable video decoding unit. Real-time 1280??720@25fps MPEG-2/MPEG-4/RealVideo decoding is achieved for on-line video streams. The SoC is fabricated in 0.13um single-poly eight-metal CMOS technology with die size of 6.4mm * 6.4mm. To achieve low...
In this paper, a functional model of SystemC-based MPEG-2 decoder is presented, which is of heterogeneous multi-IP-cores and hybrid-interconnections. Considering the application-specific features into the design flow, three important aspects are analyzed, including function partition, parameter sharing, and interconnection topology, which are the key technical difficulties in the system level design...
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