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Soft error is one of the major threats for resilient computing. Unlike SRAM soft error, which can be effectively protected by ECC, Flip-Flop soft error protection can be costly. We observe that flip-flops/latches can have asymmetric soft error rates when storing different logic values. This asymmetry can be used in conjunction with the different signal probabilities of registers in a design. In this...
A Carbon Nanotube field-effect transistor (CNFET) is a promising alternative to a traditional metal-oxide-semiconductor field-effect transistor (MOSFET) to overcome the “Power Wall” challenge. However, CNFETs are inherently subject to much larger process variation and thereby they can incur a significant design cost to build high-performance processors. Particularly, the large register files (RF)...
Quantum-dot cellular automata (QCA) are nano-scale devices for implementing logic circuits. The disadvantage of QCA circuits is that its layout determines the timing of the circuit. This is the “layout = timing” problem in QCA circuits. Null convention logic (NCL) has been proposed as a solution to this problem. However the asynchronous registers used in NCL are bulky and require a large number of...
Manual place-and-route method in handling structured datapath placement usually requires long design cycles and high design cost. To minimize the human effort in placing cells, Integrated Circuit Compiler (ICC) has been introduced to help user in automate place and route with its powerful embedded placement algorithm. A structured datapath design contains repeating dataflow logics, which is highly...
The widespread acceptance of high-level synthesis as a mainstream tool mostly depends on its tight integration with the following RTL-to-GDSII design flow. A key aspect is the handling of so-called engineering change orders (ECOs), i.e. minor changes required to fix small functional bugs or meet performance requirements late in the design cycle. Traditional high-level synthesis has attempted to optimize...
This paper presents an adiabatic register file based on improved CAL (Clocked Adiabatic Logic) circuits, which can operate in a single-phase power clock. All the circuits except for the storage cells use improved CAL circuits. The storage cell is based on the conventional memory one. For a comparison, a conventional register file is also realized. Full-custom layouts are drawn, which is realized using...
In this work, different combinations of low power techniques like multi-voltage, multi-threshold and clock gating, are applied on a general design candidate, an 8 bit RISC machine, to arrive at the optimal design combination which consumes minimum power and delivers maximum performance. A new metric called criticality rank is introduced to assign the different modules of design the multiple supply...
Clock-gating and power-gating are the most widely used solutions for reducing dynamic and static power. They can be potentially integrated so that clock-gating conditions can be used to control the power-gating circuitry thus also reducing static power. This integration becomes however difficult when applied in an industrial design flow. Even if both clock and power- gating are supported by most commercial...
A 32times32 register file based on dual transmission gate adiabatic logic (DTGAL) is implemented with TSMC 0.18 mum process. The energy of all nodes with large capacitances including storage cells can be well recovered without non-adiabatic loss. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. The results show...
Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way that the clock-gating information can be used to drive the control signal of the power-gating circuitry, thus providing additional leakage minimization conditions w.r.t. those manually inserted by the designer. This conceptual...
A 32 times 32 register file based on complementary pass-transistor adiabatic logic (CPAL) has been fabricated with chartered 0.35 mum process. All the circuits except for the storage cells employ CPAL circuits. The storage cell is based on the conventional memory one. For comparison, a conventional 32 times 32 register file is also embedded in the chip. Full-custom layouts are drawn. The energy and...
The purpose of TAFT fault tolerance studies conducted at CNES is to prepare the space community for the significant evolution linked to the usage of COTS components for developing spacecraft supercomputers. CNES has patented the DMT and DT2 fault-tolerant architectures with 'light' features. The development of a DMT/DT2 testbench based on a PowerPC7448 microprocessor from e2v is presented in this...
Although QCA (quantum dot cellular automata) has been introduced as a new kind of technology for over a decade, it still continues to be so and its merits and flaws are yet under study for future practical use. One of the problems of this technology is the dependency of its circuit timing to its layout. An asynchronous design methodology for QCA has been offered to solve this problem. The proposed...
This paper compares readout powers and operating frequencies among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM. The conventional 8T SRAM has the least transistor count, and is the most area efficient. However, the readout power becomes large and the cycle time increases due to peripheral circuits. The 10T single-end SRAM is our proposed SRAM, in which a dedicated inverter...
Analysis of the techno-economic conditions warranting currently existing deployments of 1 Gb/s (1G) Ethernet passive optical networks indicates clearly the requirement for a support of legacy equipment, allowing carriers to take advantage of already deployed 1G ONUs while increasing the channel capacity for some customers. This calls for a complete coexistence of 1G and 10 Gb/s (10G) equipment, sharing...
A CMOS 24-bit Block Floating Point Digital Signal Processor chip for Sonar applications is described. The device integrates data and program memory, two arithmetic processing elements, and address generator in a single chip providing a performance improvement of up to ten times that available using standard DSP devices for Sonar signal processing. The device has been implemented on a 1.4 micron two...
In this paper a 2 micron CMOS, MICROPROGRAMMABLE SIGNAL PROCESSOR CORE (SPC) is described, intended as the number crunching unit in Harvard-type digital signal processors. It contains a 16??16 bit Booth multiplier, a 40-bit accumulator, a 32 bit extractor, a format-adjuster, and a 3-port registerfile. Its projected 100 ns. throughput rate makes it highly suitable for applications like HiFi Audio,...
The complexity of integrated-circuit chips produced today makes it feasible to build inexpensive, special-purpose subsystems that rapidly solve sophisticated problems on behalf of a general-purpose host computer. This paper contributes to the design methodology of efficient VLSI algorithms. We present a transformation that converts synchronous systems into more time-efficient, systolic implementations...
We consider the design of integrated circuits to implement arbitrary regular expressions. In general, we may use the McNaughton-Yamada algorithm to convert a regular expression of length n into a nondeterministic finite automaton with at most 2n states and 4n transitions. Instead of converting the nondeterministic device to a deterministic one, we propose two ways of implementing the nondeterministic...
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