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A 2-6 GHz WiMAX Low Noise Amplifier (LNA) using active inductor as shunt peaking load in resistive feedback configuration is designed in 0.13-μm CMOS process. This low noise amplifier uses a single active inductor to achieve high gain and input matching which leads to a compact circuit. The simulations show a maximum power gain (S21) of 14.18dB, minimum noise figure (NF) of 2.44dB while the input...
This work presents a 1GHz ΔΣ fractional-N PLL based on the noise filtering by FIR-embedded phase interpolator (PI). The proposed PI scheme greatly improves phase linearity by a dual-referenced interpolation and realizes FIR filtering without using multiple CPs, PFDs, and dividers. The designed fractional-N PLL shows a comparable phase-noise performance to that of an integer-N PLL. The PLL is implemented...
We present a high-efficiency transmitter based on asymmetric multilevel outphasing (AMO). AMO transmitters improve their efficiency over LINC (linear amplification using nonlinear components) transmitters by switching the output envelopes of the power amplifiers among a discrete set of levels. This minimizes the occurrence of large outphasing angles, reducing the energy lost in the power combiner...
This paper outlines the intelligence and portability requirements for future genetic analysis systems tailored to fast, low cost, and large scale population studies. Methods used in current research for DNA amplification and detection are discussed. The most significant shortcomings of current practises are their lack of the programmability required to generate different heating profiles to detect...
A CMOS 80-400 MHz 5TH order Chebyshev Gm-C low-pass filter with a unique auto tuning system is presented. The filter was designed and fabricated with TSMC 0.13-μm RF CMOS process. Experimental results show that the cut-off frequency of the filter can be tuned between 80-400 MHz, with a tuning step less than 7MHz and an average tuning error of 3.6%. The filter also realizes gain of 0-30 dB, IIP3 of...
Many architectures of transistor only simulated inductors (TOSI) have been proposed until now in literature. Exhibiting tuning possibilities, low chip area and offering integration facility, they constitute promising architectures to replace passive inductors in RF circuits. An improved CMOS active inductor topology is proposed in this paper. With a novel loss compensation scheme, frequency increase...
This paper proposes a non-linear transient model for voltage-doubler circuits. By using a novel approach to model the waveform of intermediate voltages, both the dc output voltage and power spectrum are derived. Substrate currents are included to enable accurate modelling of high power applications. The model is validated by both low and high power rectifiers in UMC CMOS 0.18 μm technology. The proposed...
This paper focuses on the frequency-down-conversion realized with a proposed Mixer topology using 4 CMOS inverters only. From simulation and using typical 0.35μm CMOS process parameters, the proposed Mixer exhibits at 900MHz under 2.5 supply voltage, the following performances: a 16.8dB conversion gain, a 23dBc-IM3 with 200mVpeak-to-peak input sinusoidal waves. The corresponding IIP3 is 10dBm for...
A multiplying delay-locked loop (MDLL) is adopted for low-jitter clock generation. This architecture overcomes the drawback of phase-locked loops (PLL) such as jitter accumulation, and maintain the advantage of a PLL for multirate frequency multiplication. The MDLL, implemented in 90-nm CMOS technology, occupies about 1 mm2 and works at 400 MHz with multiplication ratio of 4. The complete synthesizer,...
A novel low power consumption and low phase noise CMOS cross-coupled LC-tank voltage-controlled oscillator (VCO) is presented. Added negative transconductance technique is used in the proposed VCO in order to improve the phase noise of the circuit by increasing the quality factor of the tank. Furthermore, common mode double-pseudo-resistance utilized in the proposed circuit helps to achieve low power...
This work presents the design and implementation of a differential class C power amplifier (PA) in a 90 nm CMOS technology, specified to be used in a IEEE802.15.4 low power transceiver. The design is based on a PA efficiency design flow implemented in MATLAB which enables to reach very good power efficiency figures. The method is validated comparing MATLAB predicted data and post-layout SpectreRF...
A comprehensive study based on chip-package co-modeling compares the effects between flip-chip ball-grid-array (FC-BGA) and wire-bond quad-flat-nonlead (WB-QFN) packages on a front-end cascode low-noise amplifier (LNA) in a 2.45 GHz CMOS wireless local area network (WLAN) receiver. In practical applications, the established package models are used to predict the degradation of figure of merit (FOM)...
This paper presents the measured results and characterisation of a 1.2 V CMOS low phase noise quadrature output phase locked loop (PLL) with an on-chip regulated DC-DC converter. In particular, it exhibits a phase noise response of less than -115 dBc/Hz at an offset of 1 MHz from the carrier and has a tuning range of over 38%. The automatic amplitude control loop in the VCO gives the facility to trade-off...
This paper presents the design of a novel RF power amplifier (PA) suitable for modern wireless communication systems. The PA employs switching mode class-E topology to exploit its soft-switching property to achieve high efficiency. The use of another class-E stage as a driver of power stage improves efficiency and increases the capability of circuit integration. A new output power control technique...
In the wireless telecommunication systems, for increasing interest in RF switch using Complementary Metal Oxide Semiconductor (CMOS) technology, for high frequency is greatly integrated. In this paper, we use the Hafnium-dioxide material as dielectric substrate for designing a model of CMOS which is used for double-gate MOSFET in DP4T RF CMOS switch. This proposed model is compact and robust as well...
This paper proposes a new active shunt-peaked realization for MOS Current Mode Logic (MCML) based memory element. The circuit proposes the use of active inductors in shunt-peaking of MCML memory element. The technique of shunt-peaking offers a way of enhancing the performance of gates at high speed of operations. The benefit of the proposed circuit is verified by designing and simulating various MCML...
Demand of radio frequency switches using Metal-Oxide-Semiconductor (MOS) technology at high-frequencies for wireless telecommunication system is increasing drastically. This paper presents the results for the development of a cell library that includes the basics of the design parameters for n-MOS transistor and p-MOS transistor to design a RF CMOS switch. The cell library design includes the properties...
This paper presents a low power all-digital phase locked loop (ADPLL) with power optimized digitally controlled oscillator (DCO). In this paper, the power optimization procedure of DCO is proposed for low power ADPLL. The procedure is based on simple equations about relationship between control bits and power dissipation. To validate the procedure, DCO has been designed and fabricated using 0.13μm...
In this paper, a fully integrated CMOS receiver front-end for 2.4-GHz Band IEEE 802.15.4 standard in a 0.18-μm CMOS technology is presented. It is comprised of a low-power CMOS LNA including a common-gate stage with modified input matching and active balanced down-conversion mixer which uses the current bleeding technique and an extra LC filter to improve the noise figure (NF) and conversion gain...
A fully integrated Phase-Locked Loop (PLL) as a clock generator is described in an advanced 32nm CMOS technology. Features include adaptive bandwidth architecture, automatic frequency calibrator (AFC), a sub-1V V/I converter operation, feedback control to minimize charge-pump current mismatch, and a fully integrated loop filter. The whole PLL measures power consumption of 1.6mW when VCO oscillates...
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