The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Recently, high-resolution TDCs have gained more and more popularity due to their increasing implementation in digital PLLs, ADCs, jitter measurement and time-of-flight measurement units. Similar to ADCs, existing architectures of TDCs can be divided into several categories: flash TDCs, pipeline TDCs, and SAR TDCs. The highest achievable time resolution of a TDC is mainly limited by the CMOS gate delay...
This paper presents a high resolution two-step gated-ring oscillator (TSGRO) time-to-digital converter (TDC) in an all digital phase-locked loop (ADPLL). TSGRO-TDC consists of a coarse step and a fine step gated-ring oscillator (GRO) TDC to achieve a high resolution. An edge aligner is used in the fine step GRO-TDC to enhance a first-order noise shaping property. A meta-stability free selection logic...
A DC-DC converter with an embedded digital controller is implemented in 40 nm CMOS. The converter including the ADC, decimator, digital filter, and DPWM occupies 0.7 mm2 of which the area occupied by the output drivers is 0.6 mm2. It achieves >90% efficiency at 200 mA load.
A digital PWM voltage mode controller integrated circuit (IC) for high-frequency dc-dc switching converters achieving virtually minimum possible, i.e. optimum, output voltage deviation to load transients is introduced. The IC is implemented with simple hardware, requiring small silicon area, and can operate as a single-phase or a two-phase controller. To minimize the area and eliminate known mode...
A 0.18 μm CMOS digitally controlled DC-DC buck converter is presented. An all-digital 8 b frequency-domain ΔΣ ADC is used for the feedback path, and a 9 b segmented digital PWM is used for power stage control. A regulated output voltage accuracy of 1% and maximum efficiency of 94% is achieved with less than 14 mVpp ripple and a settling time of 100 μs for a 300 mA load transient.
This paper presents the design of a double-sampling split ΣΔ-modulation analog-to-digital converter with cross noise-coupling. Double-sampling is used to achieve high conversion speed and low power consumption. To tackle the problem of quantization noise folding due to path mismatch, a fully floating bilinear integrator is used. Then the quantization noise is cross-coupled between two identical ΣΔ-modulators...
A digital resolution enhancement technique for time-to-digital converters (TDC) is proposed. This involves a simultaneous multi-channel measurement of a time-interval with low-complexity TDCs of varying resolutions. The coarse outputs of each converter are then digitally post-processed to obtain a single result whose precision is much better than that of any individual converter. A prototype system...
A novel 2-dimension Vernier Time to digital converter (TDC) is presented. The proposed architecture reduces drastically the number of delay stage required by linear TDCs minimizing the power consumption and the area of the design. A 7 bits TDC prototype realized in 65 nm CMOS technology is presented. The chip has a resolution of 4.8 ps with a power consumption of 1.7 mW at a conversion rate of 50...
Through the review and analysis of traditional and some recently reported conversion methods in SAR A/D converters, high speed, high resolution and low power approaches for SAR A/D converter are discussed. Based on SMIC 65 nm CMOS technology, two typical low power methods reported in previous works are validated by circuit design and simulation. Design challenges and considerations of high speed SAR...
Through the research on charge redistribution SAR A/D converter, three energy-efficient capacitor arrays are discussed in this paper. The switching energy of the traditional architecture, charge sharing architecture, capacitor splitting architecture and two-step architecture capacitor arrays is derived and analyzed. Based on SMIC 65 nm CMOS process, 10-bit SAR A/D converters of all these architectures...
The deterministic blurring and noising in pictures captured by a camera with CCD/CMOS sensor can be fairly simulated as the true image transmission through some kind of ISI channel, with specific 2D impulse response (blurring) and consequently through certain random IECS-ML channel (noising). Hence for purposes of image restoration we can use the maximal a posteriori probability (MAP) criterion based...
The paper describes a four-order delta-sigma modulation (DSM) with 15 levels quantizer which is used in a 24-bit 44.1-kHz sample-rate audio digital-to-analog converter (DAC). An odd level quantizer has been chosen instead of an even level to reduce quantization noise. The noise transfer function (NTF) is designed to have the zeros optimally in order to increase DR. The peak SNR of the DSM is about...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here a 12 bit 30 MHz analog to digital converter using a pipelined architecture. It is composed by ten 1.5 bit sub-ADC with a final 2 bit flash...
In this paper, a 12-bit 50MHz Pipelined Low-Voltage ADC is presented, which consists of 8-stage-pipelined low resolution ADCs and a 4-bit flash ADC. Several critical technologies are used to guarantee the resolution and high sampling and converting rate such as 1.5bits per stage conversion, digital correction logic, gain-boosted telescopic OTA and so on. Finally the whole system is taped out in SMIC...
A new structure of switched-capacitor AID converter is described, in which the effects of amplifier offsets and charge injection are compensated. Compared to a 1st ordre structure, the use of a second order scheme allows a substantial reduction in the conversion time. Experimental results, obtained on circuits fabricated using a CMOS technology, indicate that 15 bit accuracy is easily achievable.
A stereo D/A converter for digital audio applications is presented which obtains 16 bit resolution from a one bit converter, using a code conversion technique based upon oversampling and noise shaping. Linear-phase low-pass filtering is implemented in the code converter to allow simple analog output filtering.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.