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Due to increasing integration densities and the emergence of nanotechnology, especially reliability and power related design aspects become critical for chip design. Since the arising problems are enforced by high circuit temperatures, the need for a possibility to model thermal behavior of a system in an accurate and physically correct way becomes inevitable. Hence, in this paper VulcaNoCs, a SystemC-based...
Different models have been proposed for modeling the IV-characteristics of diodes. In this paper we present a simple model, which describes both the IV- and the temperature characteristics of a SOI-pin-diode and can be used for different diodes types. It is well known that the DC-characteristics of a diode can be approximated by the simple Shockley-equation. However, when a more exact modelling of...
Most bipolar-transistor compact models incorporate some level of self-heating capability in order to determine the impact of thermal effects on circuit performance. Techniques for predicting mutual-thermal-coupling effects, however, are not readily available within most commercial CAD platforms. Presented in this brief is a technique which allows for the easy modification of design-kit-supplied models...
In the paper a new nonlinear compact thermal model of power MOS transistors based on the Cauer network is proposed. The analytical description of the model and the method of the model parameter estimation are presented. The accuracy and usefulness of the model is verified experimentally for the trench MOS transistor MTD20N06V at its various cooling conditions.
In response to the continually increasing appetite for bandwidth, most transistor technologies have recently made great strides towards higher cutoff frequencies: Silicon MOSFETs, SiGe HBTs, InP-based HEMTs and a variety of InP -based HBTs all show cutoff frequencies fT and/or fMAX exceeding 300 GHz, and in some cases approaching 800 GHz. Proponents of various technologies have stated that the development...
The behavior of a discrete ESD protection diode during a system level ESD pulse was simulated and compared with a time resolved measurement of the real diode. The simulation results for ESD destruction level, location of the damaged zone inside the diode, and the slope of the voltage drop are very close to the measured data. Also a sudden voltage drop caused by the 2nd thermal breakdown was predicted...
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