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For modern complex designs it is impossible to fully specify design behavior, and only feasible to verify functionally meaningful scenarios. Hardware Trojans modifying only unspecified functionality are not possible to detect using existing verification methodologies and Trojan detection strategies. We propose a detection methodology for these Trojans by 1) precisely defining “suspicious” unspecified...
High dV/dt immunity is desired for isolated gate driving of next generation fast switching power devices. This requires the on-chip isolation transformer to have a small capacitive coupling between the coils. Therefore, in this paper, on-chip transformers with solid ground shield (SGS) and patterned ground shield (PGS) structures are proposed and studied. Simulation results show that the SGS achieves...
A substrate coupling analysis and simulation flow for high frequency CMOS system on chip design is presented. It's a straightforward method that can be directly adopted by designers as it only requires commercial design tools. Full chip level simulation including substrate, interconnect parasitics and package is provided in any stage of the design process. A 5 GHz CMOS LNA in the presence of an 88...
On-chip coding provides a remarkable potential to improve the energy efficiency of on-chip interconnects. However, the logic design of the encoder/decoder faces a main challenge: the area and power overhead should be minimal while, at the same time, decodability has to be guaranteed. To address these problems, we propose the concept of approximate coding, where the coding function is partially specified...
As a process technology is scaling, a reliability problem that may cause a failure in the functionality of the digital circuit becomes an important issue in System-on-Chip (SoC) design. This importance leads to the studies on fault diagnosis and tolerance. In this paper, we propose a static and analytical technique for fault diagnosis focused on the digital circuit. Gate level fault analysis is completed...
Despite great advances in technology, and design and verification tools, it is still impossible to create fully automated IC design flow that would produce working SoC designs with minimal human intervention. Instead, IC are designed and verified by using myriad of (often) non-compatible tools and design flows that are manually interrupted and adapted at will. In this paper some of the practical flow...
Since integrating memory blocks on-chip becameaffordable, embedded logic analysis has been employed duringpost-silicon validation and debugging. Failing traces obtainedthrough embedded logic analysis can be used to understand functionaldesign errors, a problem that has been studied extensivelyover the past decade. In this paper, we show that post-processingfailing traces using a computational approach,...
Network-on-Chips (NoCs) are needed to interconnect the cores which are processors and memories in Systems on Chips (SoCs). For designing new NoCs, highly accurate simulation and efficient design procedure are desired. In this paper, we present C-based RTL design method for circuit switched NoC in which RTL structure of NoC is directly described in dataflow C coding style and a fast simulation and...
Mutation Analysis (MA) is a fault-based simulation technique that is used to measure the quality of testbenches for mutant detections where mutants are simple syntactical changes in the designs. A mutant is said living if its error effect cannot be observed at the primary outputs. Previous works mainly focused on the cost reduction in the process of MA, because the MA is a computation intensive process...
In order to gain market share in today's competitive high-tech industry, fast time-to-market (TTM) is one of the key factors for the success of a product. Since pre-silicon verification cannot be applied exhaustively as the size and complexity of the integrated circuit design increases, post-silicon validation becomes crucial to capture bugs and design errors that escape from the pre-silicon verification...
Multi-core architecture has emerged as the primary architectural choice to achieve power-efficient computing in microprocessors and SoCs. Power gating is indispensable for system power and thermal management and well suited for multi-core architectures. However, checking the power integrity (such as electromigration and voltage drop) of large gated power delivery networks (PDNs) presents a significant...
Designing aliasing-free space support hardware for built-in self-testing in very large scale integration circuits and systems is of immense significance, specifically due to the design paradigm shift in recent years from system-on-board to system-on-chip. This paper develops an approach to designing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips...
Today, electronic devices are increasingly employed in different fields, including safety- and mission-critical applications, where the quality of the product is an essential requirement. In the automotive field, on-line self-test is a dependability technique currently demanded by emerging industrial standards. This paper presents an approach employed by STMicroelectronics for evaluating, or grading,...
With the increase in the design complexity of MPSoC architectures, estimating power consumption is very complex and time consuming at lower level of abstraction. We propose a methodology using ArchC named Power-ArchC for a fast high-level estimation of processor power consumption. Power values are obtained by an instruction level power characterization at gate level. The requirements for power evaluation...
This paper presents a new type of a more complete system verification method, which combines a high-level verification methodology based on verification methodology manual (VMM) techniques for functional simulation and system-on-a-programmable-chip (SOPC) techniques for board-level verification, effectively improve the adequacy and reliability of verification and validation efficiency. This paper...
Power gating is one of the most effective ways to reduce leakage power by shutting off the idle blocks in a system-on-a-chip. However, a current surge occurs when the gated blocks wake up from sleep mode, causing voltage fluctuations on the power rails, which is called ground bounce effect. In this paper, input vector control method is used to reduce the ground bounce. Genetic algorithm is applied...
Synchronizers play a key role in multi-clock domain systems on chip. Traditionally, improvement of synchronization parameters with scaling has been assumed. In particular, the resolution time constant (tau) has been expected to scale proportionally to the gate delay 'FO4'. Recent measurements, however, have yielded counter-examples showing a degradation of tau with scaling. In this paper we describe...
An investigation was performed into the cause of unexpectedly low CDM performance of a 65nm SOC LNA. The main culprit was found to be STI diode overshoot due to the fast CDM current rise time. Solutions included replacing the STI diodes with gated diodes and with incorporating a new type of secondary clamp.
We study diagnosis of segments on speedpaths that fail the timing constraint at the post-silicon stage due to manufacturing variations. We propose a formal procedure that is applied after isolating the failing speedpaths which also incorporates post-silicon path-delay measurements for more accurate analysis. Our goal is to identify segments of the failing speedpaths that have a post-silicon delay...
Optimizing blocks in a System-on-Chip (SoC) circuit is becoming more and more important nowadays due to the use of third-party Intellectual Properties (IPs) and reused design blocks. In this paper, we propose techniques and methodologies that utilize abundant external don't-cares that exist in an SoC environment for block optimization. Our symbolic code-statement reachability analysis can extract...
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