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Multi-core system is becoming the next generation embedded design platform. Heterogeneous and homogeneous processor cores integrated in Multiple Instruction Multiple Data (MIMD) System-on-a-Chip (SoC) to provide complex services, e.g. smart phones, is coming up in the horizon. However, distributed programming is a difficult problem in such systems. Today, only in very few MIMD SoC designs we can find...
Integrated Modular Avionics (IMA) architecture provides means for integrating multiple safety-critical applications on a shared hardware in an airborne system. Error free data transfer between different modules of an IMA cabinet is an issue of critical importance. ARINC 659 has proven to be one of the most comprehensive standards for intra-cabinet data transfer within an IMA cabinet of commercial...
This work presents the design methodology and the optimal FPGA implementation of a hardware video interface that can be used in any embedded system with microprocessors or microcontrollers for direct connection to a VGA compatible monitor. The design level is lowered to schematic details, which offers more optimization possibilities than any hardware description language. Such a visual design was...
The need of critical applications has derived in the development of several techniques that aim to guarantee system operability. The vast majority of these systems own a microprocessor to control its functionality. Thus, system reliability largely depends on the proper function of the microprocessor. This article presents a state of the art in the techniques for reliable microprocessor architectures...
Parallel computing is an important trend of embedded system. One possible response to increasing requirements in computational power is to distribute tasks over various processors and let these processors operate in parallel. Soft-core processors and FPGAs require low Non-Recurring Engineering costs to develop such multi-processors systems. Furthermore, certain FPGAs allow dynamic partial run-time...
An asynchronism problem between High-Speed DAC Chips in some multi-channel systems is analyzed. And, a method to solve this problem is proposed: Finding out the difference between clocks of each DAC, then compensating through data based on the difference in order to synchronize them. At the end, a diagram is proposed to solve the problem with this method in FPGA.
The present paper describes a technique for ensuring re- liable softcore processor implementation on SRAM-based field programmable gate arrays (FPGAs), which can handle the effects of single event upsets (SEUs). We propose the triple modular redundancy (TMR) scheme coupled with dynamic partial reconfiguration to remove SEUs from the configuration memory of the FPGA. Although the FPGA is subject to...
Multiprocessor platforms are gaining markets as a solution to boost general performance of processor beyond technological limitations that are present in single processors chips, Multi-processor in embedded systems also have a future in particular with applications like SDR(Software Defined Radio) where both high performance and high adaptability are required. Cryptographic algorithms implementation...
In the field of RNA secondary structure prediction, the Zuker algorithm is one of the most popular methods using free energy minimization. However, general-purpose computers including parallel computers or multi-core computers exhibit parallel efficiency of no more than 50% on Zuker. FPGA chips provide a new approach to accelerate the Zuker algorithm by exploiting fine-grained custom design. Zuker...
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circuits on FPGAs (field-programmable gate arrays). Building on dynamic synthesis for single-processor single-thread systems, known as warp processing, thread warping improves performances of multiprocessor systems by speeding...
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