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In this work, the impact of impedance mismatch between on-die CMOS drivers and driven transmission lines on electromigration (EM) and Joule-heating failure mechanisms has been qualitatively studied. Signals corrupted by the impedance mismatch were experimentally measured within a 45-nm CMOS technology ULSI test chip. The signals' current waveforms were obtained using a SPICE simulator. These voltage...
We present the first sensor network architecture to monitor integrated circuits (IC) thermal and energy activity. The sensor network consists of a set of simple gates, which are superimposed over the actual design of any IC. The sensing network and the actual IC design are completely disjoint in order to enable their simultaneous operation. Since the delay of gates is proportional to their temperature,...
Laboratory measurement and acquisition system based on the LabVIEW virtual instrumentation software package, applied to automated procedure for integrated circuit parameter testing, is presented in this paper. Described software controlled procedure is performed on CMOS inverter integrated circuit HCF 4007 UB Hardware configuration of developed solution includes data acquisition card PCI NI 6251 and...
A mostly digital variable-rate continuous-time ΔΣ modulator is presented with power dissipation, output sample-rate, bandwidth, and peak SNDR ranges of 8 to 17 mW, 0.5 to 1.15 GHz, 3.9 to 18 MHz, and 67 to 78 dB, respectively. The IC is implemented in a 65 nm CMOS process with an active area of 0.07 mm2.
In this paper research output cascades for integrated circuits and microsystems-on-chip with silicon-on-insulator structures (SOI) of executed after traditional CMOS process and with the use of double control by connecting to the subchannels areas in SOI MOS transistors.
Two modified regulated cascode amplifier (RCA) structures are presented that reduce the output compliance voltage requirements of conventional RCA. One structure utilizes a push-pull amplifier to enhance output resistance whereas the other structure incorporates a level shifter in the conventional RCA structure. P-SPICE simulations have been used to validate the proposed structures at ??0.6 V for...
We demonstrated essential technological components for wafer-scale integrated CMOS nanotube circuits such as inverters, NAND, and NOR logic gates: 1.The full-wafer-scale synthesis and transfer of massively aligned carbon nanotubes, and device fabrication on 4 inch substrates 2. In-depth device study and tuning, and extensive doping study for the first wafer-scale integrated CMOS nanotube circuits...
The authors investigated an EMC macro-model of the CMOS logic inverter gate, named LECCS-I/O that consists of linear equivalent circuit and current sources. This paper modifies the macro-model by adding another current source to express the short-circuit current in the inverter. The macro-model was determined from SPICE calculations of impedance and power current by using a device model of an inverter...
Conventional side-channel attacks which exploit the dynamic power consumption of CMOS devices to extract secret information from cryptographic devices are well established. The presence of an additional side channel utilising scattered electromagnetic emissions has previously been suggested, though a practical demonstration of the effect on cryptographic hardware has not been published. This paper...
This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.
Simultaneous switching noise (SSN) is an important issue for the design and test and actual ICs. In particular, SSN that originates from the internal logic circuitry becomes a serious problem as the speed and density of the internal circuit increase. In this paper, an on-chip monitor is proposed to detect potential logic errors in digital circuits due to the presence of SSN. This monitor checks the...
This document presents a compilation of results from tests performed by iRoC Technologies on SER induced by alpha particles on SRAM memories for technology nodes from 180 nm to 65 nm. The aim of this study is to establish the variation of sensitivity with technology node for SEU and MCU, and to analyze the possible influence of different designs and technological parameters at a given technology node.
The soft-error vulnerability of flip-flops has become an important factor in IC reliability in sub-100-nm CMOS technologies. In the present work the soft-error rate (SER) of a 65-nm flip-flop has been investigated with the use of alpha-accelerated testing. Simulations have been applied to study the flip-flop SER sensitivity in detail. Furthermore, an easy-to-use approach is presented to make an accurate...
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
With the event of nanoscale technologies, new physical phenomena and technological limitations are increasing the process variability and its impact on circuit yield and performances. Like combinatory cells, the sequential cells also suffer of variations, impacting their timing characteristics. Regarding the timing behaviors, setup and hold time violation probabilities are increasing. This article...
The minimum operating voltage (Vmin) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (VT) of MOSFETs. The Vmin, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs...
We present a generic method for analyzing the effect of process variability in nanoscale circuits. The proposed framework uses kernel and a generic tail probability estimator to eliminate the need for a-priori density choice for the nature of circuit variation. This allows capturing the true nature of the circuit variation from a few random samples of its observed responses. The data-driven, non-parametric,...
As mainstream processing technology advances into 65 nm and beyond, many factors that were previously considered secondary or insignificant, can now have an impact on chip timing. One of these factor is inversed temperature dependence (ITD). As supply voltage continues scaling into sub-IV territory, delay-temperature relationship can be reversed on some cells, meaning that device switching time may...
A novel methodology for accurate and efficient static timing analysis is presented in this paper. The methodology is based on finding a frequency domain model for the gates which allows uniform treatment of the gates and interconnects. It is shown that despite the highly nonlinear overall gate model, a frequency domain model of the gate with the model parameters, gate moments, as functions of the...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
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