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In this paper, we architect large-scale SRAM arrays with monolithic 3D (M3D) integration technology. We introduce M3D-based SRAM arrays with three different ways of integration: M3D-R (vertical routing-only), M3D-VBL (vertical bitline), and M3D-VWL (vertical wordline). We also apply M3D-based SRAM arrays to last-level caches: tag arrays for eDRAM LLCs and data arrays for SRAM LLCs. The proposed LLCs...
The wire-length of vertically stacked ICs plays a vital role. The wire-length is minimized by using differential evolutionary algorithms withIBM Benchmark inputs. Moreover this wire length is minimized with the respect to the length of the Through Silicon via (TSVs). As a result, the wire-length has been minimized using this algorithm with various parameters. Experimental result shows that the total...
In this paper, the performance of GSG co-planar waveguide (CPW) type transmission line on silicon interposer and stacking memories by through-silicon-vias (TSVs) are analyzed. The high conductor loss of fine lines will cause the impedance varying with frequency and make the reflection loss minor. Furthermore the flat attenuation of such fine line will result in low distortion waveforms and have better...
In this paper, we propose a 2D and 3D interconnect network based on a Mesh-of-Clusters (MoC) topology for the implementation of an efficient Field Programmable Gate Arrays (FPGA) architecture. Proposed MoC-based FPGA architecture presents a new hierarchical Switch Box (SBs) and depopulated intra-cluster interconnect based on the Butterfly-Fat-Tree (BFT) topology. Long routing wires which span multiple...
In this paper, we propose a 2D and 3D interconnect network based on a Mesh-of-Clusters (MoC) topology for the implementation of an efficient Field Programmable Gate Arrays (FPGA) architecture. Proposed MoC-based FPGA architecture presents a new hierarchical Switch Box (SBs) and depopulated intra-cluster interconnect based on the Butterfly-Fat-Tree (BFT) topology. Long routing wires which span multiple...
Three-dimensional integrated circuits (3-D IC) are available through the die-stacking and through-silicon-via (TSV) technologies. The 3-D IC using the TSV brings the performance improvement through the minimization of wire length and footprint area. However, the 3-D ICs have many challenges for power delivery network design due to larger supply currents and longer power delivery paths compared to...
Electromigration (EM) has become a key reliability concern for nanometer IC designs. For 3D ICs, higher current density/temperature and TSV-induced thermal mechanical stress further exacerbate the EM issue compared to 2D ICs. In this paper, we analyze the root causes of EM for 3D IC signal nets, with consideration of current density, temperature, and TSV-induced thermal mechanical stress. We develop...
This paper proposes comprehensive solutions to the clock tree synthesis problem that provides pre-bond testability for 3D IC designs. In 3D ICs, it is essential to stack only good dies by testing the individual dies before stacking. For the clock signaling, the pre-bond testing requires a complete 2D clock tree on each die. The previous work enables the pre-bond testability by allocating specially...
Three dimensional integrated circuits (3D ICs) are currently being developed to improve existing 2D designs by providing smaller chip areas and higher performance and lower power consumption. However, before 3D ICs become a viable technology, the 3D design space needs to be fully explored and 3D EDA tools need to be developed. To help explore the 3D design space and help fill the need for 3D EDA tools,...
The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing through silicon vias (TSV) for vertical connectivity is investigated with a cycle-accurate RTL simulator. The physical latency and area impact of TSVs, switches, and the on-chip interconnect is evaluated to extract the maximum signaling speeds through the switches, horizontal and vertical network links. The...
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