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SOI FinFET transistors have emerged as novel devices having superior controls over short channel effects (SCE) than the conventional MOS transistor devices. However despite these advantages, these also exhibit certain other undesirable characteristics such as corner effects, quantum effects, tunneling etc. Usually, the corner effect deteriorates the performance by increasing the leakage current. In...
We present a study of the conductance of quantum point contacts fabricated in AlGaN/GaN and Si/SiGe heterostructures. The investigated devices differ for typology (split gates and etched devices, respectively) and for the resulting potential profiles. We observe conductance quantization in multiple of 2e2/h units with superimposed anomalous plateaus and/or structures suggesting that correlation effects...
The authors have demonstrated a simple method to precisely control the number and the position of nanometer-scaled Ge quantum dots (QDs) embedded in SiO2 or Si3N4 tunnel barriers via thermally oxidizing pre-patterned nanostructures. A single Ge QD in the core or twin Ge QDs near the edges of the nanotrench could be realized by modulating the initial nanostructure's dimensions and the spacer's materials...
Stacked multichannel transistor architectures were proposed recently which possess very attractive electrical characteristics on low leakage current and high driving current per layout area. However, due to complex manufacturing process, the process variation effect is inevitable and whose impact is unknown. Therefore, this study investigates the impact of process variation on 15-nm-gate stacked multichannel...
We study the coherent transport of electrons through a uniformly doped Silicon quantum wire in the presence of one impurity in the channel at room temperature using fully 3D Non-Equilibrium Green's Functions technique. The potential of the single impurity, assumed to be attractive (a donor), is self-consistently calculated via Poisson equation coupled with Schro??dinger equation in the effective mass...
Memristors are the two-terminal components that complete the symmetry between the fundamental circuit variables, and they are highly suitable for bioinspired and neural-network-based computational systems due to their inherent memory effect. In this paper we present a fabrication technique that uses only Complementary Metal Oxide Semiconductor (CMOS) processing steps and conventional photolithography,...
We describe the integration of p-i-n structures for single-ion implant detection with p-type channel-stop regions to eliminate parasitic leakage currents in n-MOS structures while maintaining a single-ion detection capability. The structures are configured for the assembly of a metal-oxide-semiconductor (MOS) spin-qubit architecture based on phosphorus donors in silicon. The detection method is based...
We have developed a full quantum transport simulator for p-type Si nanowire field effect transistors based on the k??p Hamiltonian. The NEGF formalism was employed for transport calculation and the self-consistent calculations were performed. We have constructed the Hamiltonian in the modespace, with its size greatly reduced compared to the full Hamiltonian. A computationally demanding problem of...
This paper describes a 180 nm CMOS thin film SOI technology developed for RF switch applications. For the first time we show that the well-known harmonic generation issue in HRES SOI technologies can be suppressed with one additional mask. Power handling, linearity, and Ron*Coff product are competitive with GaAs pHEMT and silicon-on-sapphire technologies.
Silicon-on-insulator technology utilizing very high resistivity handle wafers demonstrates sufficient performance for many cellular handset requirements. Technologies with either thin or thick device layers show promise. Thick-SOI prototype single pole six throw switch (SP6T) P-0.1dB of about 40 dBm and -75 dBc harmonic at 35 dBm output have been demonstrated at 900 MHz. Thin-SOI Ron-Coff product...
In this paper, we present a self-consistent and 3D quantum simulator for Si-nanowire transistors based on the Wigner function model and multidimensional Schrodinger-Poisson algorithm. To achieve a sufficient numerical accuracy for calculating subthreshold current, we introduced a third-order differencing scheme for discretizing the drift term in the Wigner transport equation. By comparing with semiclassical...
In order to decrease bias voltages in IMOS devices we have proposed a new IMOS structure with Si-Ge/Si heterostructure channel in this paper. In comparison with previously reported, single gate SOI IMOS and SGOI IMOS structures, this device can provide higher reduction in the source voltage as well as in threshold voltage. Moreover, the proposed structure provides considerable reduction in off-state...
After forty years of advances in integrated circuit technology, the scaling of Silicon Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has entered the nanometer dimension with the introduction of 90 nm high volume manufacturing in 2004. Presently at 45 nm going to 32 nm node in 2009, the latest technological advancement has led to low power, high-density and high-speed generation of microprocessors...
The silicon pillar thickness effect on vertical double gate MOSFET (VDGM) fabricated by implementing oblique rotating ion implantation (ORI) method is investigated. For this purpose, several silicon pillar thicknesses tsi were simulated. The source region was found to merge at tsi < 57 nm, forming floating body effect. The electron-hole concentration along the channel and the depletion isolation...
The static and large-signal behaviour of a new model for a submicron partially-depleted (PD) body-tied (BT) silicon-on-insulator (SOI) MOSFET was recently shown to give excellent agreement with measurements. Here, we complete the model validation with a detailed study of its small-signal capabilities up to a frequency of 50 GHz. Additionally, a new direct procedure is described enabling the extraction...
A simple, area and power-loss efficient, portable and robust ESD protection method for DC/DC converters is presented. The method is based on MOS transistors operating in normal mode, replacing the snapback based design methods. Measurement results of a prototype fabricated on silicon showed good agreement with simulation and are reported.
The ESD sensitivity of 65-nm fully depleted SOI MOSFETs (with thin silicon body) used as output buffer devices is studied. A detailed electrical investigation is carried out in order to classify the observed failure modes and mechanisms. We propose a new failure criterion that allows us to univocally identify the device failure. Finally, we analyze the impact of device geometry and strain engineering...
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