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A 16-bit (5+11) segmented digital-to-analog converter (DAC), based on a voltage mode R-2R topology that is able to derive high resolution and high performance, in terms of INL and DNL, and less area and power consumption comparing with conventional DACs. It is designed and simulated in 65nm CMOS process. A current compensating technique is used to achieve good dynamic performance. The 16 bit R-2R...
In this work a comprehensive SPICE model is demonstrated for perimeter-gated single photon avalanche diodes (PGSPAD) fabricated in commercial 0.5 µm CMOS process. This model simulates the trigger of an avalanche event of PGSPAD due to photon absorption, along with the quenching behavior. It also simulates the I–V characteristic, where the breakdown voltage can be modulated with applied gate voltage...
In this paper, a new approach toward the design of a memristor based nonvolatile static random-access memory (SRAM) cell using a combination of memristor and metal-oxide semiconductor devices is proposed. Memristor and MOSFETs of the Taiwan Semiconductor Manufacturing Company's 180-nm technology are used to form a single cell. The predicted area of this cell is significantly less and the average read–write...
This paper presents a new CMOS current-feedback operational amplifier based on the adoption of the MOS tube in order to improve slew-rate. The cascode circuit was used to decrease the influence of power supply. Resistance feedback was used in the output stage to improve its load driving capability. Simulation results of the CFOA using BSM3's 0.25um CMOS process parameters with PSPICE, result in a...
Much excitement has been generated over the potential uses of chalcogenide glasses and other materials in circuits as “memristors” or as non-volatile memories. The memristor is a fourth passive two terminal electronic device, postulated by Leon Chua in 1971 and rediscovered in 2008. Our Conductive Bridge Memristor (CBM) changes its resistance in response to current passing through it by building up...
This paper presents a novel current-controlled current conveyor transconductance amplifier (CCCCTA). The design considerations is realized in CMOS technology based on the AMS's 0.35 μm CMOS process. The performances are examined through HSPICE simulations. The proposed element consists of a balanced differential-pair CCCII circuit and operational transconductance amplifier (OTA). It provides less...
The CMOS transistor pair of Seevinck and Wassenaar is reviewed. Beside the properties previously reported it is shown by calculating the effective SPICE parameter LAMBDA that the channel length modulation is improved. The analytic derivation is verified by simulations of both P and N type pairs. It is also shown that for small effective gate voltages a negative incremental resistance is obtained for...
This paper presents a highly linear Operational Transconductance Amplifier (OTA) that combines two linearization techniques, one with adaptive biasing of differential pairs and second with using of resistive source degeneration. OTA has ??0.9 v power supply and consumes 456 ??w. Improvement of adaptive bias circuit has enhanced the CMRR to 135 dB in DC. OTA has been simulated with TSMC 0.18 ??m technology...
A modified regulated cascode structure having high output swing capability is presented. This structure is used in the implementation of a current mirror. The current mirror possesses wide input and wide output swing capabilities, suitable for low voltage operation. P-SPICE simulations at 0.25 ??m CMOS technology validate the proposed current mirror for currents from 30 nA to 220 ??A, at 1 V with...
An ultra low-power CMOS low-dropout regulator (LDO), consuming only 680-nA quiescent current with fast transient response and 10-mA load capability, is proposed in this paper. It is designed in a 0.35-μm CMOS technology and verified by HSPICE simulations. With the proposed internal frequency compensation method, the LDO can be stabilized without minimal requirement of equivalent-series-resistance...
Two modified regulated cascode amplifier (RCA) structures are presented that reduce the output compliance voltage requirements of conventional RCA. One structure utilizes a push-pull amplifier to enhance output resistance whereas the other structure incorporates a level shifter in the conventional RCA structure. P-SPICE simulations have been used to validate the proposed structures at ??0.6 V for...
A novel structure, based on balanced differential-pair, is proposed to implement the CMOS CCCII with negative intrinsic resistance at port X. HSPICE simulations, based on the AMS's 0.35mu CMOS process, are conducted, which certainly confirm the occurrence of negative resistance. To demonstrate its capability, a two-phase current-mode oscillator is synthesized based on two lossless integrators. As...
A wide bandwidth CMOS realization of high performance dual output second generation (CCIIplusmn) and third generation (CCIIIplusmn) current conveyors are presented. Both second and third generation current conveyors have the advantages of a wide current and voltage bandwidths, controlled intrinsic resistances at port X, Y and Z. We have developed an optimization program, thanks to Heuristic methodology...
In this paper, we proposed a neuron MOS current mirror with a transimpedance amplifier. A conventional circuit is composed of a voltage amplifier and resistances. However, the resistance voltage drop makes operating range narrow. A proposed circuit is composed of a transimpedance amplifier. And the proposed circuit has high current copy accuracy and wide operating range. The proposed circuit is designed...
Compact diode models normally available in commercial simulators like Spectre or HSPICE do not scale the series resistance with P-N distance. The standard diode models scale with drawn area, assuming the current is vertical. However the diodes used for ESD protection in CMOS are operating as lateral diodes, so the resistance should scale with width, not area. This is a serious problem for circuit...
RF non-quasi-static effect and interconnection delay effect are not considered in a conventional BSIM3v3 RF model. For modeling these effects, an improved RF SPICE model for 0.13 mum MOSFET is developed by including the scalable inductances and using the gate resistance scaling equation. This improved model is validated by finding better agreements with measured S-parameters up to 40 GHz at various...
A novel translinear CMOS current controlled conveyor II(CCCII) is presented. The principle of the CCCII circuit and its implementation in CMOS process are described. Then, the application of CCCII to active simulated inductance and active filter is presented. Results of PSPICE simulation verify the feasibility of the novel CCCII both in circuit implementation and application.
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
In this work, the bulk-gate controlled circuit to improve the power supply ripple ratio (PSRR) of a Low Dropout Regulator (LDO) which deteriorates due to lowering power consumption is proposed. Designing with 0.25 mum CMOS process, the simulation results by HSPICE shown that the proposed circuit provides a high performance of PSRR even though 1/10 of the power consumption is reduced compare to the...
Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend...
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