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This paper describes a new methodology of construction of the internal activity block of an ICEM-CE model of an FPGA based on a predictive approach using the estimation tools of the dynamic power and the static timing proposed by the manufacturer of the integrated circuit.
A high-throughput architecture of the CCSDS 122.0-B-1 image compression standard is proposed. The architecture uses a novel memory organization in order to reduce the total memory operations and the number of the individual memories allowing operation without external memories. The architecture has been implemented on space grade and commercial FPGA Device. It achieves 136 MSamples/sec on space grade...
This paper describes a new methodology of construction of the internal activity block of an ICEM-CE model of an FPGA based on a predictive approach using the estimation tools of the dynamic power and the static timing proposed by the manufacturer of the integrated circuit.
This paper presents an satellite camera imaging system using area CCD based on FPGA. FPGA was adopted to act as a center unit to generate timing logic signals of the CCD and control the A/D converter, etc. The three-wire serial interface is used to communicate with the management and control system on the satellite. The image data of the CCD is coded by the imaging system and converted to the required...
Timing analysis in embedded systems has focused mainly on the Worst-Case Execution Time (WCET) in the past. This was (and still is) important to make guarantees for the application of the system in safety critical environments. Today, two reasons call for a slightly changed perspective. Firstly, the complex and often unpredictable internal structure of modern system-on-chip architectures prohibits...
This paper describes a cloud-based digital design environment for ASIC and FPGA. We call it CloudV. CloudV is built using open-source as well as homegrown EDA software tools. The ultimate goal of CloudV is to reduce the design costs by relying on cloud infrastructure and on collaborative design. Currently, CloudV v 1.0 allows students to gain hands-on experience in digital ASIC design tasks covering...
Compared with the infrared focal plane array (IRFPA) based on amorphous silicon (α-Si), IRFPA based on vanadium oxide (VOx) has the advantages of big temperature coefficient, low noise and so on. Therefore, it is believed that VOx IRFPA has important application in both military and civil field. In this paper, the designs of driving module and signal processing module of VOx IRFPA are proposed. Firstly,...
SAKURA-G (Side-channel AttacK User Reference Architecture — G) board equipped with two Spartan-6 FPGAs was developed for physical attack experiments against a cryptographic circuit as a successor to SASEBO-GII. In this work we developed a clock manipulator for SAKURA-G, which generate glitch noises to provoke malfunctions on a cryptographic circuit. By using the DCM (Digital Clock Manager) and PLL...
There are many simulators to evaluate the performance of computer architecture, however they are commonly based on Software Architecture Model Execution (SAME). Due to hardly implement parallel execution on multicore platforms, their simulation speeds are slow. To solve the problem, we propose to improve simulation speed of SAME simulators on FPGA using SystemC synthesizable timing models. First,...
As the core of video processing system in industrial cameras, the quality of charge-coupled devices has an immediate effect on the reliability of system. In order to achieve the requirement of high quality and reliability in industrial applications, the performance of CCD must be validated during selection and working. An innovative CCD quality verification system was introduced in this paper, and...
The paper introduces a new multi-core SoC platform designed for industrial automation applications with mixed criticality. The applications are written in SystemJ language. The multi-core platform consisting of three different types of cores is implemented in a SoC that contains a standard dual-core ARM and a FPGA, which is used to run the critical part of the system. The platform is fully customizable...
The ubiquitous computing era is characterized by wide deployment of resource constraint devices. Secure communication between such devices encounters a big challenge due to their resource limitation. The lightweight cryptographic algorithms are developed to address this challenge. In this work, implementation of LBlock, a lightweight encryption algorithm is investigated in Altera DE1 FPGA board. The...
In Positron Emission Tomography (PET) and Quantum Optics, the quality of the reconstructed images is directly proportional to the quality of the employed coincidence detectors, which provide important timing information about the location of the emitted nuclear particles. This paper proposes a new circuitry, called precise coincidence detector (PCD). It consists of two RS latches, is of low complexity,...
This paper focus on the implementation of configurable linear feedback shift register (CLFSR) in VHDL and evaluates its performance with respect to logic, speed and memory requirement in FPGA. Behavioral implementation of CLFSR in VHDL is configurable in terms of number of bits in the LFSR, the number of taps, positions of each tap in the shift register stage and seed value of LFSR. The target device...
Current processors have gone through multiple internal optimization to speed-up the average execution time e.g. pipelines, branch prediction. Besides, internal communication mechanisms and shared resources like caches or buses have a significant impact on Worst-Case Execution Times (WCETs). Having an accurate estimate of a WCET is now a challenge. Probabilistic approaches provide a viable alternative...
In this work, we designed a Visitor Counting Machine (VCM) in terms of power efficient circuit using family of three different IO Standards which are LVTTL, Mobile DDR, HSUL 12. These three different IO Standards are compared with each other on the basis of Clock power, Logic power, Signal power, IOs, Leakage power and Total power consumption to search the most power efficient one. In order to find...
In order to apply the CPU to the control system for the renewable energy plant which is usually installed in the isolated place, there are a lot of issues e.g. the cooling, the power conservation and the parts exchange with the device life cycle. The undetectable dangerous error of the control system is also a big issue for such the isolated plant with the long term operation, because it causes the...
This paper subsumes the concept of Internet of Things on a Tera Hertz RAM on the 40nm FPGA. Time analysis has been performed on a Tera Hertz RAM. This produces correspondingly higher speeds as compared to any other form of RAM available. The main focus has been on studying the slack for various frequencies. Slack is a kind of error and should be as low as possible. We aim to find that optimum condition...
Fixed-width multipliers are widely used in digital signal processing (DSP) applications such as finite impulse response filter (FIR), fast Fourier transform (FFT) and discrete cosine transform (DCT). Baugh-Wooley multiplier is a preferred choice for the realization of 2's complement multiplication operation used in these applications. This paper presents the hardware realization and performance evaluation...
This paper investigates the limits of adaptive voltage scaling (AVS) applied to commercial FPGAs which do not specifically support voltage adaptation. An adaptive power architecture based on a modified design flow is created with in-situ detectors and dynamic reconfiguration of clock management resources. AVS is a power-saving technique that enables a device to regulate its own voltage and frequency...
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