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During the design of embedded systems, many design decisions have to be made to trade off between conflicting objectives such as cost, performance, and power. Approximate computing allows to optimize each objective, yet for the sake of accuracy. This means that a functional flaw is allowed to produce an error as long as this is small enough to maintain a feasible operation of the system or guarantee...
For the efficient filter implementation reconfigurability and low power have always been the main concerns. This paper introduces two new low power and high speed reconfigurable parametric equalizer designs. These designs are based on the row bypassing multipliers which are implemented using carry save adder (CSA) and ripple carry adder (RCA). The primary power reduction is procured by turning off...
Software Defined Radio (SDR) devices are becoming increasingly popular due to their support for mode-, standard- and application-flexibility. At the same time however, the energy consumption of such devices typically suffers from the use of reconfigurable real-time platforms which are known to be severely power hungry. In this work we therefore show how to use tools and techniques developed by the...
Reconfigurability and low power have always been the main concern for the efficient filter implementation. This paper introduces two new low power and high speed reconfigurable Hilbert transformer designs. These designs are based on the carry save adder (CSA) and ripple carry adder (RCA) based row bypassing multipliers. The primary power reduction is procured by turning off adders when the multiplier...
Arithmetic Logic Units are one of the vital unit in general purpose processors and major source of power dissipation. In this paper we have demonstrated an optimized Arithmetic and Logic Unit through the use of an optimized carry select adder. Carry select adders have been considered as the best in their category in terms of power and delay. In this context a full adder optimized in terms of power...
Run-time reconfigurable computing systems can offer increased flexibility when compared with traditional systems, a feature which can make them attractive for space-borne computing applications. This flexibility can allow a system to adapt to changes in operating conditions, such as reductions in available power, reductions in available resources (wither due to increases in task deployment, or due...
This paper presents the low power compressor based Multiply-Accumulate (MAC) architecture for DSP applications. In VLSI, highly computed arithmetic cells including adders and multipliers are the most copiously used components. Efficient implementation of arithmetic logic units, floating point units and other dedicated functional components are utilized in most of the microprocessors and digital signal...
As the characteristic dimension shrinks to the nanometer scale, Multiplication unit in modern processors will become increasingly vulnerable in consuming much power and area. Existing logical optimization for placement and routing approaches in multiplication unit primarily focus on reducing the overhead and power consumption of FPGA's. However, our analysis shows that, the proposed method plays an...
Multiply and Accumulate is the main component of the DSP System, which is the major block for power consumption and decides the speed of the overall system due to its complex operation. Hence in most of the DSPs, it lies in the critical path. In this work, Low power MAC architecture has been proposed by examining the critical paths and the hardware complexities. Proposed is a generic architecture...
An antilog is the inverse function of a logarithm. Today, conventional use of the term “antilog” has been replaced in mathematics by the term “exponent”. The binary logarithm is often used in the field of computer science and information theory because it is closely connected to the binary numeral system, in the analysis of algorithms and Single-elimination tournaments etc. So an efficient system...
Design and implementation of a low-power and low-cost booth-shift/add multiplexer-based singed multiplier is presented. The main blocks of the circuit are constructed with some simple low-power structures. It includes multiplexer-based booth encoder and singed shifter blocks, multiplexer-based Manchester adder, an optimized and compact structure of control unit, and a low-power structure for full...
We describe the physical design and exploration methodology to optimize 3-dimensional (3D) heterogeneous Tree-based FPGA (HT-FPGA) by introducing a break-point at a particular tree level interconnect to optimize the speed, power consumption and area. The ability of the flow to decide a horizontal or vertical partitioning of the multilevel programmable tree network based on design specifications is...
The key problems in designing of VLSI circuits are high power consumption, larger area utilization and delay which affect the speed of the computation and also results in power dissipation. In general speed and power are the essential factors in VLSI design. For solving the issues, a new architecture has been proposed. In the proposed system, the two high speed multipliers, Modified booth multiplier...
Interconnect has become preponderant in many aspects of digital circuit design, namely delay, power and area. This effect is particularly true for FPGAs, where interconnection is often the most limiting factor. Multiple-valued logic allows to reduce interconnections, within logic cells and between them, hence effectively mitigating the impact of interconnections. In this paper we propose a new look-up...
The push for mobility in all areas of information technology brings the need to develop systems that perform their functions even if they have limited access to power sources (batteries, solar panels, etc.). The same systems however are expected to improve their performance significantly when the power requirements are no longer a problem. This paper proposes an adder architecture for use in digital...
Reconfigurable architecture gives the advantage of both high performance and high flexibility. However power consumption is also an important criterion which determines the efficiency of the reconfigurable architecture to be used in data intensive applications like cryptography, multimedia and signal processing. This paper analyzes a coarse grained reconfigurable adder which can be dynamically reconfigured...
Interconnections play a crucial role in todays deep sub-micron designs because they dominate the delay, power and area. This is especially critical for modern million-gates FPGAs, where as much as 90% of chip area is devoted to interconnections. Multiple-valued logic allows for the reduction of the required number of signals in the circuit, hence can serve as a means to effectively curtail the impact...
A multiplierless discrete cosine transform (DCT) architecture is proposed to improve the power efficiency of image/video coders. Power reduction is achieved by minimizing both the number of arithmetic operations and their bit width. To minimize arithmetic-operation redundancy, our DCT design focuses on Chen's factorization approach and the constant matrix multiplication (CMM) problem. The 8times1...
In this paper, a kind of pseudo Gray code presentation of test patterns based on accumulation generators is presented and a low power test scheme is proposed to test computational function modules with contiguous subspace in VLSI, especially in DSP. If test patterns from accumulators for the modules are encoded in the pseudo Gray code presentation, the switching activities of the modules are reduced,...
A hybrid FPGA consists of island-style fine-grained units and domain-specific coarse-grained units. This paper describes an approach to estimate the power consumption of a set of hybrid FPGA architectures. The dynamic power consumption of the fine-grained units is obtained using standard FPGA tools, and the coarse-grained units using standard ASIC tools. Based on this approach, the dynamic power consumption...
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