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Memory hierarchy in current generation computers is formed by keeping registers inside, cache on or outside the processor and virtual memory on Hard disk. The principle of locality of reference is used to make memory hierarchy work efficiently. In recent years various advances have been made to improve the cache memory performance on the basis of hit rate, latency, speed, replacement policies and...
The growing concern in tracking, identification and localization systems has turn Radio Frequency Identification (RFID) technology into a mainstream in scientific research. In this technology, the phenomena known as the tag collision problem is becoming increasingly important, since it leads to a wastage of bandwidth, energy, and an increase in identification delay. There- fore, anti-collision protocols...
Complex multiplications are the backbones of almost all Digital Signal Processing (DSP) algorithms and several other scientific applications. Complexity Reduction of these operations at architectural level or algorithmic level can certainly save the chip area, which ultimately can be a driver parameter for selection of power or speed optimized architectures. Improvement in these performance parameters...
In this paper, a 6-bit 320-MS/s successive approximation register analog-to-digital converter (SAR ADC) is presented. The 2-bit/cycle technique and tri-level based charge redistribution technique are utilized to achieve high conversion rate and reduce the hardware cost. The proposed ADC is designed and implemented in a 65-nm CMOS process. Simulation results show that it accomplishes 48.52-dB SFDR,...
Hardware Trojans pose a difficult threat to hardware systems due to the difficulty in their identification. In many cases, the differences observed between Trojan and Trusted chips can be very small. This research explored the feasibility of using low-precision test equipment in order to identify malicious modifications to circuits programmed to Field Programmable Gate Arrays (FPGAs). Examination...
Technical innovation drives the low power consumption requirements in ASIC design. This paper presents a SD card controller, in which two asynchronous units (BIU and CIU) are included for lower power structure. Adding low power mode to finite state machine makes this controller to shut down if no data or command is transferring for a long time. Only one FIFO is used to store temporary data in order...
Sequential linear decompressors are inherently efficient and attractive for compressing test cubes with many don't cares. The test cubes are encoded by solving a system of linear equations. In continuous decompression, typically a fixed number of free variables are used to encode each test cube in a “one-size-fits-all” manner. The non-pivot free variables used in Gaussian elimination are wasted when...
A set of reference designs suitable for our student design projects was developed and tested. The purpose is to make them available for students to choose the ones suitable for integration into their projects with confidence. All the reference designs are available on our website. Some of those that are intended for embedded control applications are described in this paper. They are reference designs...
The paper deals with the problem of test data volume, decompressor hardware overhead and test application time of scan based circuits. Broadcast-based test compression techniques can reduce both the test data volume and test application time. Pattern overlapping test compression techniques are proven to be highly effective in the test data volume reduction and low decompressor hardware requirements...
ZigBee technology is being embedded in a range of applications up to smart energy, healthcare, and telecommunication services. In this paper, we present a voice transmission system, one of telecommunication value-added services, based on the low-rate ZigBee networks. We design a model to perform a sensor role as a member of ZigBee networks in addition to providing the cost-effective voice transmission...
Hardware realization of decimal arithmetic operations is becoming a necessity in commercial, financial and internet-based applications. Exponentiation is a frequently used but time-consuming operation for these applications. Usually, squaring and multiplication are combinedly used to simplify exponentiation. Though research in decimal multiplication has received a lot of attention, the exploration...
Nanoscale VLSI design faces unprecedented reliability challenges in the presence of prevalent catastrophic defects, soft errors and parametric variations. In this paper, I propose a group of error-detecting/correcting-code(EDC/ECC)-based self-checked/corrected/timed circuits for logic robustness and performance scalability in nanoscale VLSI design. Compared with the existing techniques, the proposed...
Differential Power Analysis (DPA) is a powerful Side-Channel Attack (SCA) targeting as well symmetric as asymmetric ciphers. Its principle is based on a statistical treatment of power consumption measurements monitored on an Integrated Circuit (IC) computing cryptographic operations. A lot of works have proposed improvements of the attack, but no one focuses on ordering measurements. Our proposal...
The aim of this work is to demonstrate the advantages and disadvantages of different ways of implementing subtraction and thresholding in the processing of digital images. The four different systems will be analysed: first in a PC computer with a Borland C++ program, second with an embedded microprocessor programmed in C++, third with a DSP also programmed in C++, and finally with a hardware designed...
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