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Producing reliable, integrated systems is becoming extremely difficult due to the increasing variability and uncertainty inherent in advancing fabrication technologies; the worsening effects of various wear-out mechanisms; and environmental disturbances (e.g., soft errors due to radiation). Solutions to this problem centering on traditional approaches involving redundant resources are likely to be...
A power-on-reset circuit of novel simple structure and high reliability is proposed. The circuit has been designed in 0.5 mum bipolar CMOS technology. The simulation was performed with 0.5 mum CSMC process model and Cadence Spectre and the results show that the circuit has a stable and reliable performance. With the differences of supply voltage's ramp rate, temperature and process, the change of...
A low cost method to prioritize circuit rehabilitation efforts is described and illustrated with a decade of field failure data, covering over 18,000 km of cable installed over three decades.
This paper describes an ESD verification methodology that is applied at several points in the design process. By identifying ESD reliability hazards at each step in the design flow, the amount of redesign needed to address ESD reliability issues is greatly reduced. The checker efficiently computes power bus parasitic resistances, allowing it to be used during floor planning when the library is unavailable;...
We present a practical, systematical method for the evaluation of the soft error rate (SER) of microelectronic devices. Existing methodologies, practices and tools are integrated in a common approach while highlighting the need for specific data or tools. The showcased method is particularly adapted for evaluating the SER of very complex microelectronic devices by engineers confronted to increasingly...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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