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The cost of integrated circuits increases with the complexity and integration density. This has led designers to consider testing from the design phase; that's what we call DFT (design for testability). In this paper, we propose a DFT solution, based on technique of IDDQ measuring current, by incorporating a Built-In Current sensor, whose function is to detect power consumption of different circuits...
High temperature in test process may invalidate a test due to extra delay, or even damage the circuit under test. Therefore, a thermal-safe test can avoid undesirable yield loss due to the extra delay induced by high temperature. Traditional high level test synthesis approaches just improve hierarchical testability of circuits and minimize test application time. If the thermal effects are ignored,...
In earlier, Fault Analysis (FA) has been exploited for several aspects of analog and digital testing. These include, test development, Design for Test (DFT) schemes qualification, and fault grading. Higher quality fault analysis will reduce the number of defective chips that slip past the tests and end up in customer's systems. This is commonly referred to as defective parts per million (DPM) that...
Testability modeling has been performed for many years. Unfortunately, the modeling of a design for testability is often performed after the design is complete. This limits the functional use of the testability model to determining what level of test coverage is available in the design. This information may be useful to help assess whether a product meets a requirement to achieve a desired level of...
This paper presents a design for test (DFT) methodology focused on high precision analog circuits using trimming methodology. A simulation technique called trimming analysis was derived from the production test process and is used for simulation-based verification of the circuit performances including trimming network and trimming algorithm. The virtual trimming by joint simulation of the test procedure...
Test response compaction for integrated circuits (ICs) with scan-based design-for-testability (DFT) support in the presence of unknown logic values (Xs) is investigated from a combinatorial viewpoint. The theoretical foundations of X-codes, employed in an X-tolerant compaction technique called X-compact, are examined. Through the formulation of a combinatorial model of X-compact, novel design techniques...
Functional test sequences are often used in manufacturing testing to target defects that are not detected by structural test. However, they suffer from low defect coverage since they are mostly derived in practice from existing design-verification test sequences. Therefore, there is a need to increase their effectiveness using design-for-testablity (DFT) techniques. We present a DFT method that uses...
This paper describes a low cost test technique for testing Analog-Mixed Signal and RF load boards used in ATE (Automatic Test Equipment). The paper describes the development and application of a software tool for automatic analysis and test generation for mixed signal and RF circuits on Device Interface Boards (DIB). DIBs are essential components for testing ICs and they contain mixed-signal and RF...
Functional verification is a major hurdle in todaypsilas design flow. Current technologies are not meeting the challenges imposed by design complexity. Dark corners detection is still the simulation bottleneck in the verification process. While functional verification remains not sufficiently mature, test techniques are improved and completely automated, accordingly complex circuits can be tested...
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient errors during system operation are no longer restricted to memories but also affect random logic, and a robust design becomes mandatory to ensure a reliable system operation. Self-checking circuits rely on redundancy to detect...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. A possible solution to alleviate this problem in the future could consist in using fault tolerant architectures to tolerate manufacturing defects. In this paper, we analyze the conditions that make the use of a classical triple modular redundancy (TMR) architecture...
The continuous characteristic of the parametric faults spectrum, the process variations and their masking effects are major difficulties limiting the development of efficient test generation for parametric faults. Moreover, there is a need for accurate test metrics to quantify the quality of a test set and to determine whether the testability is adequate. An analog test metric called parameter fault...
This paper describes the integration of a new tool for testability measurement and improvement into a design system for integrated circuits. The involved design system, CADDY (Carlsruhe Digital Design System), uses a functional description of a circuit written in a PASCAL like language and synthesizes a list of nets and real logical components. In this resulting structure all storing elements are...
The question ``why design for testability?'' will be answered by discussing some existing test philosophies. Exhaustive testing, functional testing and structural testing will be treated, also with regard to their usefulness for VLSI circuits. There is no general agreement on how to design for testability. Various approaches exist, and each has its specific applications. Some of these approaches will...
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