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This paper presents a new type of coarse-grained reconfigurable architecture (CGRA) for the object inference domain in machine learning. The proposed CGRA is optimized for stream processing and a correspondent programming model called dual-track model is proposed. The CGRA is realized in Verilog HDL and implemented in SMIC 55 nm process, with the footprint of 3.79 mm2 and consuming 1.79 W at 500 MHz...
Coarse-grained reconfigurable architecture (CGRA) aims to provide satisfying solutions in terms of both efficiency and flexibility. However, to meet the ever increasing performance demand for multimedia applications, the scale of CGRAs should be larger enough to contain more computation resources for higher processing performance. In this paper, we present a hybrid-priority configuration cache supervision...
In this paper, a configuration context reduction method for coarse-grained reconfigurable architecture (CGRA) is proposed. The proposed method exploits the structure correlation of computation tasks that are mapped onto CGRA and reduce the redundancies in configuration context. Experimental results show that the proposed method can averagely reduce the configuration context size up to 57% and speed...
In this paper, we have scaled-up a Coarse-Grain Reconfigurable Array (CGRA) in specific widths to evaluate matrix-vector multiplication and radix-4 64-point Fast Fourier Transform (FFT) algorithms. The evaluation of different CGRAs is based on complexity in application mapping, performance and area utilization. Reducing the product development time and achieving higher reliability has always been...
Coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attention due to their performance and flexibility. However, their applications have been restricted to domains based on integer arithmetic since typical CGRAs support only integer arithmetic or logical operations. This paper introduces approaches to mapping applications onto CGRAs supporting both integer and floating-point...
This paper presents three different control techniques to couple a Coarse-Grain Reconfigurable Architecture (CGRA) with a generic RISC processor. In the architecture under study the CGRA, i.e., a coarse-grain array, works as co-processor and is used to accelerate a kernel selected by the application developer. The array is meant to perform the data processing operations of the kernel, while the RISC...
This article discussed about modeling of uCOS real time operation system kernel which is widely used in embedded system field based on CSP, describing the behavior of uCOS from the higher abstract layer, to help us understand how uCOS working better, also provide foundation of further working on uCOS includes model checking and soundness verification on uCOS. This article focused on the task scheduling...
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