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To mitigate the total power consumption in any circuit, ASICs or FPGAs, various conventional power gating techniques has been adopted depending upon the need of the application, dynamically controlled power gating procedure is one such power gating technique which can be used to reduce the total leakage power consumption of the circuit during the runtime. It can be applied on the real time application...
We reconsider guarded evaluation as a means to reduce FPGA dynamic power consumption. We augment and evaluate guarded evaluation as proposed in [1] after different stages of the FPGA CAD flow. Guarding later in the flow provides more feedback to the algorithm and yields a more effective cost-benefit analysis of newly added signals. Numerical results show that guarding later in the flow yields slightly...
The development of sustainable and durable ultra-low-power SoC calls for flexibility integration in the design flow. Reconfigurable logic circumvents the intrinsic low speed performances of software processing in microcontrollers but FPGA fabrics to be embedded suffer from a high power overhead compared to dedicated ASICs. We show that, by combining a power-oriented implementation using multi-VT,...
In this paper, we exploit the ambipolarity property of double gate devices such as DG-CNTFETs to design a new 4:1 multiplexer, with a significant reduction in circuit complexity with respect to conventional CMOS-based multiplexers for equivalent functionality. Based on Pass-Transistor Logic, it demonstrates performance improvement of up to 3× concerning Power-Delay-Product reduction, as compared to...
In high frequency FPGAs with technology scale shrinking and threshold voltage value decreasing and based on existing large numbers of unused resources, leakage power has a considerable contribution in total power consumption. On the other hand, process variation, as an important challenge in nano-scale technologies, has a great impact on leakage power of FPGAs. Reconfigurability of FPGAs makes an...
In this paper, we propose a method for the multi-objective mapping of applications onto matrix-based nanocomputer architectures. These architectures are composed from reconfigurable logic cells interconnected according to a given topology. The power consumption and data propagation delay of each cell depend on its internal function, e.g. NAND, OR, etc. By taking into account these cell characteristics,...
The finite state machine (FSM) needed for the low power system pulse frequency modulated (PFM) mode in a buck converter is usually asynchronous because the fast clock needed for a synchronous FSM consumes too much power, or is maybe even not available. However, the implementation, verification and testing of a asynchronous FSM is complicated compared to an synchronous one. This paper presents a concept...
The design mainly discussed the low power consumption cymometer's circuit implementation plan. It is based on the most practical digital system simulation VHDL language. Then through compilation, simulation, downloaded to the FPGA device up with MAX+PLUS software, investigated cymometer's practicable. And through the use of electronic circuit simulation EWB software verified cymometer's correct in...
The performance of field-programmable gate arrays (FPGAs) has been significantly improved due to a new process technology. However, several problems have arisen in the new generation FPGAs. Specifically, the issue of power consumption is a serious issue, because FPGAs have many routing resources. We report on the improvement of both the FPGA routing structure and electronic design automation (EDA)...
Per-flow queuing is believed to be an effective approach to guarantee Quality of Service (QoS) in high performance routers. However, its brute-force implementation consumes a huge amount of memory and is not scalable as the number of flows increases. Dynamic Queue Sharing (DQS) mechanism, in which a physical queue is dynamically created on-demand when a new flow comes and released when the flow temporarily...
Leakage power contribution in total power has been more than dynamic one in Deep Sub-Micron (DSM) technologies because of Vth decremsent. Furthermore, process variation has become as the main challenge in those technologies. In this paper, an optimized process variation-aware Field Programmable Gate Array (FPGA) placement algorithm has been proposed for leakage power reduction without any architecture...
Routing switches are one of key challenges in FPGA Design field. There are several works performed on routing switch design, but the effect of wires in interconnection rarely considered. In this work, switch design methodologies have been investigated. Among these methods, a modified routing switch is proposed which has less delay and power with notice the wires effects.
Security devices are vulnerable to differential power analysis (DPA) that reveals the key by monitoring the power consumption of the circuits. In this paper, we present the first DPA attack against an FPGA implementation of the camellia encryption algorithm with all key sizes and evaluate the DPA resistance of the algorithm. The Camellia cryptographic algorithm involves several different key-dependent...
Interconnections play a crucial role in todays deep sub-micron designs because they dominate the delay, power and area. This is especially critical for modern million-gates FPGAs, where as much as 90% of chip area is devoted to interconnections. Multiple-valued logic allows for the reduction of the required number of signals in the circuit, hence can serve as a means to effectively curtail the impact...
This paper considers the problem of lookup table (LUT) based FPGA technology mapping for power minimization in combinational circuits. The problem has been previously proved to be NP-hard, and hence we present an efficient heuristic algorithm, PowerMap_er. This paper describes a technique that reduces power consumption by reducing the edge count in mapped network. The purpose of this technique is...
As technology scales, leakage power shares a dominant part in the total power dissipation of the chip and reaches up to 50% or even higher at elevated temperatures in 45 nm technology. Leakage power dissipation is especially problematic for FPGAs due to their reconfigurable nature and large number of inactive resources. Body biasing is an efficient technique to reduce leakage current which has been...
A hybrid FPGA consists of island-style fine-grained units and domain-specific coarse-grained units. This paper describes an approach to estimate the power consumption of a set of hybrid FPGA architectures. The dynamic power consumption of the fine-grained units is obtained using standard FPGA tools, and the coarse-grained units using standard ASIC tools. Based on this approach, the dynamic power consumption...
In this paper, a reconflgurable multi-precision Radix-4 Booth multiplier structure is presented. The reconfig- urable 8 x 8 bit multiplier unit can be cascaded to form a multiplier that can adapt to variable input precision requirements. The number of bits can be extended by concatenating more stages together. For example, four 8 x8 bit units can be used to build a 16 x 16 bit Booth multiplier. In...
This work proposes a new DPWM architecture that takes advantage of FPGA's advanced characteristics, especially the DLLs (Delay-Locked Loop) present in almost every FPGA. The proposed DPWM combines a synchronous (counter-based) block with an asynchronous block for increased resolution without unnecessarily increasing the clock frequency. The experimental results show an implementation in a low cost...
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