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This paper presents a novel switching scheme for an ultra-low energy charge-redistribution digital-to-analog converter (DAC) to be used in successive-approximation register (SAR) analog-to-digital converter (ADC). The proposed scheme employs unit capacitors for voltage sampling and charge redistribution. Compared with previously published capacitive DAC which uses the same unit size of capacitor array,...
A new switch control method for a capacitive DAC architecture has been presented. This has been implemented to make a successive approximation register (SAR) ADC more energy efficient. By splitting the capacitor array into two equal halves and using a unity gain buffer, the proposed architecture reduces the switching energy by 97 percent compared to the conventional switching method. The proposed...
A biomedical electronics interface to detect heart signals is presented including a reconflgurable full differential fifth-order Bessel Gm-C filter and a 12 bit low-power fully differential successive approximation register analog-to-digital converter (SAR ADC). The total fully differential structure reduces the input signal noise and distortion effectively. A switch array is used in Gm-C filter to...
A 5-bit 2GS/s current-steering D/A converter for ultra-wideband (UWB) transceivers is presented in this paper. It is based on a full-binary weighted architecture and achieves better than 10-bit static linearity without calibration. The DAC occupies 0.5mm × 0.75mm in a standard 90nm CMOS technology. A spurious-free dynamic range (SFDR) of more than 30dB has been measured over the complete Nyquist interval...
Analysis and experimental results for a new switching scheme and topology for charge sharing DACs used in successive approximation register (SAR) ADCs is presented. The characteristics of the SAR algorithm are exploited to develop a switching scheme that reduces the number of required unit capacitors by nearly an order of magnitude over conventional charge sharing DACs without the aid of any additional...
This paper presents a 14-bit digital-to-analog converter (DAC) with pipelined dynamic element matching to eliminate signal-dependent distortions and achieve good linearity at high sampling frequencies. A return-to-zero output stage is developed to enhance the dynamic linearity and increase the output impedance of current sources. And a novel current source array is employed to eliminate systematic...
This paper presents a 10-bit SAR ADC using a variable window function to reduce the unnecessary switching in DAC network. At 10-MS/s and 1-V supply, the ADC consumes only 98 μW and achieves an SNDR of 60.97 dB, resulting in an FOM of 11 fJ/Conversion-step. The prototype is fabricated in a 0.18μm CMOS technology.
An ultra low-energy successive approximation (SA) Analog-to-Digital Converter (ADC) is presented. The proposed ADC uses an energy-efficient unit capacitor array having a new switching arrangement in DAC for passive charge re-distribution. Reference levels are generated sequentially to get successive bits. The proposed method is analyzed theoretically and compared with other methods. Mathematical analysis...
A successive approximation ADC based on the C2C DAC architecture is introduced. The ADC designed in a 0.18 ??m CMOS 2 Poly 4 Metal process uses a hybrid capacitive DAC combining the best of the binary weighted capacitive array and the C2C array. C2C ladder based architectures are very attractive for implementation because of its small area, high speed and low power consumption. However a major drawback...
Hybrid implementation of DACs using a combination of thermometer coded DACs together with binary weighted DACs to achieve high conversion performance have been reported. This work compares and analyzes between 12-bit and 14-bit DACs. It is found that the speed depends on the segmentation configuration where simpler segmentation results in higher conversion speeds. The power dissipation is also dependent...
This paper describes a 12-bit 200 MHz CMOS DAC for wireless communication. The proposed DAC consists of a unit current-cell matrix for 6 MSBs and a unit current-cell matrix for 4 NSBs and a binary-weighted array for 2 LSBs. In order to ensure the linearity of DAC, a double centro symmetric current matrix is designed by using the Q2 random walk strategy. A voltage limiter circuit that limits the switching...
In this study, design of a 16-bit, 400MSPS high-speed high-resolution current steering D/A converter is described. With pipelined thermometer decoding, multi-stage synchronous latch, current-source matching array design, two-stage active cascade design, and current switch nonlinear capacitor bootstrapping compensation technologies, DAC dynamic performances at high frequency are improved. The DAC uses...
An embedded 14-bit 1-GS/s digital-to-analog converter for direct digital frequency synthesizer (DDFS) application is presented. The DAC is implemented using a segmented current-steering architecture, with the top 6 bits and the remaining 8 bits. The output stage of dual return-to-zero scheme is used to enhance the dynamic performance of spurious-free dynamic range (SFDR). The DAC core is fabricated...
In this paper, new sequence switching and layout techniques are presented for the design of high-speed high-accuracy current-steering DACs. Our new sequence switching technique - after-fabrication programmable switching - rearranges the switching sequence of current sources after chip fabrication, which will guarantee to generate an optimal switching sequence to achieve high static accuracy. With...
This paper presents a 10-bit 400 MS/s CMOS current-steering digital-to-analog converter (DAC) for video applications. The proposed DAC adapts segmented architecture, composed of 6 MSBs unary and 4 LSBs binary-weighted cells. An improved current switching scheme is developed to compensate the systematic error further. The post-layout simulation results show that the converter achieves a spurious-free...
This paper presents an energy-efficient SAR ADC which adopts reduced MSB cycling step with dual sampling of the analog signal. By sampling and holding the analog signal asymmetrically at both input sides of comparator, the MSB cycling step can be hidden by hold mode. Benefits from this technique, not only the total capacitance of DAC is reduced by half, but also the average switching energy is reduced...
This paper reports a 6-bit 220-MS/s time-interleaving successive approximation register analog-to-digital converter (SAR ADC) for low-power low-cost CMOS integrated systems. The major concept of the design is based on the proposed set-and-down capacitor switching method in the DAC capacitor array. Compared to the conventional switching method, the average switching energy is reduced about 81%. At...
This paper is concerned with the design of a high speed current steering DAC. Techniques to improve static precision are preserved while their negative influences on dynamic performance are suppressed. The prototype is implemented with the SMIC 0.13 ??m process. With an update rate of 700 Msamples/s, measurements show that the DAC achieves over 40 dB SFDR under a sampling rate of 700 Ms/s and consumes...
In this paper, an ultra-high-speed, differential current-steering mode 10-bit D/A converter is presented. The converter consists of 8-channel time division multiplexer, 5-31 ??thermometer?? decoder, fast current conversion switch, constant current source array, and other units, is processed in 0.35 ??m SiGe BiCMOS standard process technology, and has a data fresh rate of up to 1 GSPS. First, the circuit...
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