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Genetic Programming (GP) has been around for over two decades and has been used in a wide range of practical applications producing human competitive results in several domains. In this paper we present a discussion and a proposal of a GP algorithm that could be conveniently implemented on an embedded system, as part of a broader research project that pursues the implementation of a complete GP system...
Single processor architectures are unable to provide the required performance of high performance embedded systems. Parallel processing based on general-purpose processors can achieve these performances with a considerable increase of required resources. However, in many cases, simplified optimized parallel cores can be used instead of general-purpose processors achieving better performance at lower...
Soft processors are increasingly being used to host embedded systems applications on reconfigurable computing platforms such as the field-programmable gate array (FPGA). Soft processors are sequential, synchronous devices that are not capable of exploiting the concurrency available on FPGAs. We present a method for automatically synthesizing interrupt-driven binaries into custom, self-contained, circuitizable...
Tools for designing signal processing systems with their semantic foundation in dataflow modeling often use high-level graphical user interface (GUI) or text based languages that allow specifying applications as directed graphs. Such graphical representations serve as an initial reference point for further analysis and optimizations that lead to platform-specific implementations. For large-scale applications,...
A robot vision system is developed based on an intelligent image gathering card that contains an FPGA (Field Programmable Gate Array) and a DSP (Digital Signal Processor) as main calculators. Two real-time visual modules are developed through the cooperation of hardware logics on FPGA and software on DSP. First, with edge images extracted by the FPGA, a highly efficient algorithm is designed to extract...
A single-chip FPGA implementation of a vision core is an efficient way to design fast and compact embedded vision systems from the PCB design level. The scope of the research is to design a novel FPGA-based parallel architecture for embedded vision entirely with on-chip FPGA resources. We designed it by utilizing block-RAMs and IO interfaces on the FPGA. As a result, the system is compact, fast and...
Implementation of embedded systems-on-chip on modern field programmable gate arrays (FPGAs) chip is doable due to its large density. Architecture of multilevel computing focusing on its embedded processor is suggested in our project. The architecture design of embedded processor presents the challenges and opportunities that stem from the task coarse granularity and the large number of input and output...
Field-programmable gate arrays (FPGA) are drawing increasing interest because of its performance, power consumption and configurability. They execute wide range of parallelizable algorithms which changes in accordance to variations in wireless channel statistics are utilized in smart antenna array embedded systems. In this article, we've described the FPGA implementation of a QRD processor that enables...
In Embedded Systems, the calculation of RSA cryptographic operations is sometimes hard to achieve if time constraints must be observed. In the following, we present an approach to increase processing power regarding cryptographic operations using FPGA (Field Programmable Gate Array) technology. The FPGA, which is present in many designs anyway, computes parts of the operations, allowing the embedded...
Bio Informatics has emerged as one of those sciences in which if knowledge, if exploited ethically, will result in the general benefit of mankind. The enormity of DNA strand data has been revealed to be of humongous proportions. It is imperative to employ the art of parallel and distributed supercomputing in order to process such magnanimous magnitudes of data. We have deployed a scalable array of...
While parallelism and multi-cores are receiving much attention as a major scalability path, customization is another, orthogonal and complementary, scalability path which can target not easily parallelizable programs or program sections. The key assets of customization are cost and power efficiency. The key limitation of customization is flexibility. However, we argue that there is no perfect balance...
With the evolution of programmable structures, that become more heterogeneous, the process of mapping a design into these structures becomes more and more complex. Modern FPGA chips are equipped with embedded memory blocks that can be used to increase the implementation quality of the design. The paper presents a logic synthesis method based on balanced decomposition that uses the concept of r-admissibility...
Presented is a mapping of a CORDIC algorithm to a recently proposed reconfigurable array geared towards the calculation of transcedental functions. This work demonstrates that the previously introduced shift-enabled embedded reconfigurable array (ShEERA) yields speed performance very close (and better in certain cases) to that of an ASIC generated with standard cells, but with a high degree of flexibility...
This paper presents a non-monolithic top-down reconfigurable multiplier suitable for embedding in an FPGA structure. It is constructed of four individual partitions that can operate as separate multipliers but also concatenate to form a superior multiplier with increased precision and sign handling ability. The number of possible operation modes is limited in order to keep the reconfiguration overhead...
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