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A hybrid electric vehicle powered by battery and ultra-capacitor can be a solution to the rapidly changing power cycle of the vehicle on uneven terrain wherein battery satisfies long term energy and ultra-capacitor satisfies high power requirements. This paper deals with design of a control strategy that combines features of both sources and also stores energy generated during regenerative braking...
The decap leakage constitutes a significant part of total leakage in multicore processors. Leaking decap is widely used in chips to provide transient power to function blocks, and the amount of decap placed over multicore chip is determined by the worst case at design time. Considering that the decaps do not have to be kept 100% "on" when the chip is running workloads, in this paper we propose...
Delay-based Dual-rail Pre-charge Logic (DDPL) is a logic style introduced with the aim of hiding power consumption in cryptographic circuits in order to prevent Power Analysis (PA) attacks. Its particular data encoding allows to make the adsorbed current constant for each data input combination, irrespective of capacitive load conditions, which allows to design a PA-resistant circuit without routing...
Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend...
This paper describes a design flow for the circuit-level optimization of a technology. The concurrent exploration of device characteristics and library design choices leads to a more application-optimal technology. We illustrate the design flow by: 1) analyzing the impact of buffer cell design, and 2) by optimizing a 130 nm technology for low operational power.
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
A novel compact coupled planar resonator (CCPR) based VCO (voltage controlled oscillator) using mode-coupling technique was developed in response to expensive high Ceramic and SAW resonators based signal source for wireless communications. One of the problems related to the conventional Ceramic/SAW based resonators (with high Q and low phase noise) is the challenge for integration in IC form. Instead...
The next generation of wireless communication is a ubiquitous radio system concept, providing wireless access from short-range to wide-area, with one single reconfigurable and adaptive system for all envisaged radio environments. This paper presents the design approach of RCO (reconfigurable concurrent oscillator) that simultaneously generates two or more signals of different frequencies that eliminate...
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